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TMS320F28388D: EtherCAT Slave Controller: ESC_PHY_CLK output switching characteristics

Sebastian Ausserwoeger
Prodigy 220 points
Part Number: TMS320F28388D
Other Parts Discussed in Thread: DP83822H

Hi,

Since we're planning to use the F28388D's ESC_PHY_CLK output as a clock source for the EtherCAT PHYs (DP83822H), we wanted to be sure that the PHY's oscillator timing specifications are met. I'm desperately looking for the output switching characteristics (e.g. rise/fall times, jitter, etc.) of the ESC_PHY_CLK output within the TMS320F28388D datasheet but until now I wasn't able to find specific data for this output.

I would appreciate some information regarding this topic.

Thanks in advance.

Best regards,

Sebastian

  • 0
    TI__Mastermind 45606 points

    Hi Sebastian,

    We don't currently have these characteristics in our datasheet  and documentation. I will pull in someone else from our team who can provide more details on the ESC_PHY_CLK output functionality.

    Best,

    Kevin

  • 0 in reply to Kevin Allen18
    TI__Mastermind 45606 points

    Hi Sebastian,

    We don't have the requested data to share at this time. I'll note that ESC_PHY_CLK output will have dependence on the external reference clock being used in the design.

    Best,

    Kevin

  • 0 in reply to Kevin Allen18
    Prodigy 220 points

    Hi Kevin,

    thanks for the quick response. In Figure 31-10 in the Tech Ref Manual it is shown that ESC_PHY_CLK it is a direct "pass-through" signal from the 25MHz clock which is also fed to the ESC core. It is somewhat obvious, that the clock quality is mainly dependent on external clock specifications which creates the 25MHz in the first place - I totally agree.

    Now, my main concern was that the "pass-trough" structure inside the F28388D might introduce some additional delay or jitter.

    Best regards,

    Sebastian

  • 0 in reply to Sebastian Ausserwoeger
    TI__Mastermind 45606 points

    Hi Sebastian,

    Sebastian Ausserwoeger said:
    Now, my main concern was that the "pass-trough" structure inside the F28388D might introduce some additional delay or jitter.

    Understand the concern. We unfortunately don't have further data to share on the ESC_PHY_CLK out signal currently. If using a good external oscillator source you could have it directly connect to the F2838x device and Ethernet PHYs. This is what we do in the F2838x ControlCard design, with included clock buffer.

    If you haven't already I'd suggest taking a look at the clocking recommendations in section '31.2.6.2 Clocking' of the F2838x TRM also the Beckhoff Hardware Data Sheet Section I document. There's some considerations and details regarding the 25 ppm requirement for EtherCAT from Beckhoff.

    Best,

    Kevin

  • 0 in reply to Kevin Allen18
    Prodigy 220 points

    Hi Kevin,

    yeah, I've seen the solution with the clock buffer on the Control Card. The intention was to minimize system costs, since the ESC_PHY_CLK output is available on the F28388D "for free".

    Anyway, I guess we'll just have to evaluate both solutions.

    Do you expect the data on ESC_PHY_CLK timing to be available any time soon? In this case I would leave the thread open, since the issue is not really resolved yet.

    Thanks.

    Best regards,

    Sebastian

  • 0 in reply to Sebastian Ausserwoeger
    TI__Mastermind 45606 points

    Hi Sebastian,

    Sebastian Ausserwoeger said:
    Do you expect the data on ESC_PHY_CLK timing to be available any time soon? In this case I would leave the thread open, since the issue is not really resolved yet.

    I am checking with our team, but I don't expect we will have it quickly available. Sorry I can't be of more help currently.

    Best,

    Kevin