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LAUNCHXL-F280049C: About IF3 DMA of CAN module

Part Number: LAUNCHXL-F280049C


Hi,

   I am using IF3 registers with DMA mode.  My program configuration is as follow(based on "can_ex4_loopback_dma"):

1.  The DMA src Addr is CAN_IF3MCTL, and I want to move 2 words with DMA. It will move the value of CAN_IF3MCTL and CAN_IF3DATA register to  the Custom array "rxMsgData1[4]" ideally.

2. For testing, I only set Data_B bit in CAN_IF3OBS Register.

3.The result is as follow:

   CAN_IF3MCTL and CAN_IF3DATA register get the true value, and the Custom array "rxMsgData1[4]" also get the true value by DMA.

QUESTION:

1.But what surprised me was that I only set Data_B bit in CAN_IF3OBS Register. I didn't set Data_A bit or Ctrl bit in CAN_IF3OBS Register at all. Why?

2.IF I want to use IF3 registers with DMA mode, how can I  configure the CAN_IF3OBS Register and related registers of DMA?

  • In addition, I am using F28379 also, there are not DMA mode. But I found that  Data_B/Data_A/Ctrl/Arb/Mask bit of CAN_IF3OBS Register have no effect.

    I don't need to configure one of "Data_B/Data_A/Ctrl/Arb/Mask" bit when automatic IF3 update. I only configure appropriate value in CAN_IF3UPD register.It will move the message from mailbox to IF3. And I can read IF3 register by CPU(not DMA). The same as F280049C

  • Hi Lei,

    1.) From above register captures you provided, the DMA example does what it is expected to do by moving 2 words, CAN_IF3MCTL and CAN_IF3DATA. In order for DMA transaction to take place, you would have set DE3 bit in CAN_CTL register for F280049 which has DMA support.

    2.) I ran CAN test cases on 2 setups, F280049 and F28379 (with no DCAN DMA support) and just inspected IF3 after message transaction.  I could observe correct values for ARB, Control, DATA_A and DATA_B as long as IF3UPD is set to the proper mailbox.  I did not have to update CAN_IF3OBS register.  From the description, you only need IF3OBS register bit[4-0] if using DMA, so this will not be applicable for F28379:

    "The observation flags (Bits [4:0]) in the IF3 Observation register are used to determine, which data sections of
    the IF3 Interface Register set have to be read in order to complete a DMA read cycle."

    Regards,

    Joseph

  • Hi,

       Thanks for your reply!But I still have questions,may be my description is not clear.

       1).IF I want to use IF3 registers with DMA mode, I have set DE3 bit in CAN_CTL register and IF3UPD is set to the proper mailbox. But, I arbitrarily set one of "Data_B/Data_A/Ctrl/Arb/Mask" bit in CAN_IF3OBS Register,it will cause DMA transfer. I originally thought that if  I want to configure

    "DMA_configAddresses(DMA_CH5_BASE, rxMsgData,  (uint16_t *)(CANA_BASE + CAN_O_IF3MCTL));".

    I must set Ctrl bit in CAN_IF3OBS Register, but it's not. If I set anyother bit, it will trigger the DMA transfer. So, I don't know why?

      2). What I have to confirm is that:

           IF I want to use IF3 registers with Non-DMA mode, is there no need to set IF3OBS register bit[4-0] for F280049    or F28379?

  • Hi Lei,

    1.) You would still need to configure the DMA settings (example: DMA_configAddresses) if you want DMA transfers between C28x memory and IF3 registers.  CAN_IF3OBS bits[4:0] will determine data sections for DMA.  Are you saying that if you set bit 2 CAN_IF3OBS[Ctrl], you do not see any data transfer from IF3MCTL to C28memory but for the other observation bits [0,1,3,4], DMA transfer is possible?  Can you confirm?  When you set bit 2 and DMA transfer is not happening, can you poll for bit 10 [IF3SC]?

    2.) Yes, if you want to use IF3 registers in non-DMA mode, there is no need to set IF3OBS bit[4-0]. 

    Regards,

    Joseph

  • Hi,

      I am sorry. May be my description is not clear.

     

    Are you saying that if you set bit 2 CAN_IF3OBS[Ctrl], you do not see any data transfer from IF3MCTL to C28memory but for the other observation bits [0,1,3,4], DMA transfer is possible?  Can you confirm?  When you set bit 2 and DMA transfer is not happening, can you poll for bit 10 [IF3SC]?

    I have configured:

    "DMA_configAddresses(DMA_CH5_BASE, rxMsgData,  (uint16_t *)(CANA_BASE + CAN_O_IF3MCTL));

    DMA_configBurst(DMA_CH5_BASE, 4, 2, 1);

    DMA_configTransfer(DMA_CH5_BASE, 2, 0, 0);

    DMA_configMode(DMA_CH5_BASE, DMA_TRIGGER_CANAIF3, DMA_CFG_CONTINUOUS_ENABLE | DMA_CFG_SIZE_16BIT);

    DMA_setInterruptMode(DMA_CH5_BASE, DMA_INT_AT_BEGINNING);

    .......

    HWREG(CANA_BASE + CAN_O_IF3UPD) =  0x00000002;

    HWREGH(CANA_BASE + CAN_O_IF3OBS) =    CAN_IF3OBS_DATA_B;

    "

       My purpose is:

      CAN module automatic IF3 update, and enable DMA mode.  Then, two words(CAN_IF3MCTL and CAN_IF3DATA)  will be moved from IF3 to C28x memory.

       Yes, it did!I have seen the correct value of rxMsgData1[4] in CCS "Expressions". 

        But, my question is:

       According to the configuration "HWREGH(CANA_BASE + CAN_O_IF3OBS) =    CAN_IF3OBS_DATA_B;" , I didn't set CAN_IF3OBS_CTRL bit in IF3OBS, but it still executes correctly.  And I have tried:

    HWREGH(CANA_BASE + CAN_O_IF3OBS) =    CAN_IF3OBS_ARB;

    or

    HWREGH(CANA_BASE + CAN_O_IF3OBS) =    CAN_IF3OBS_DATA_A;

    or

    HWREGH(CANA_BASE + CAN_O_IF3OBS) =    CAN_IF3OBS_DATA_A;

    or

    HWREGH(CANA_BASE + CAN_O_IF3OBS) =    CCAN_IF3OBS_MASK;

    The result are all true!

    Why I can set any value(CAN_IF3OBS_ARB or CAN_IF3OBS_CTRL or CAN_IF3OBS_DATA_A or CAN_IF3OBS_DATA_B or CAN_IF3OBS_MASK) to trigger DMA? And then all of them will get the correct value!

          Thanks!

  • Lei,

    Ok, I think I understand your point.  What you are doing is configuring DMA and pointing to IF3MCTL as IF register for the transfer transaction.  You configured IF3OBS and regardless which bit you set (DATA_A or DATA_B or ARB or MASK or CTRL), you get the correct value of IF3MCTL in C28 memory.  Let me dig deeper into this and how to properly use IF3OBS in DMA mode.

    Regards,

    Joseph

  • Lei,

    I just realized this note in the description of CAN_IF3OBS:

    "Note: If IF3 Update Enable is used and no Observation flag is set, the corresponding message objects will be
    copied to IF3 without activating the DMA request line and without waiting for DMA read accesses."

    As long as you have updated IF3UPD with the message number, transfer will proceed even if IF3OBS bits[4:0] are not set.  You can also try an experiment where you do not set any bit in IF3UPD but set the IF3OBS bit 2 (or any other bits) and see if you get the DMA transfer to proceed.

    Thanks,

    Joseph

  • Hi,

       Thank you very much for your reply!

       According to your suggestion, I have experimented them. What surprised me was:

    1).

    As long as you have updated IF3UPD with the message number, transfer will proceed even if IF3OBS bits[4:0] are not set. 

    The message can be transfered from mailbox to IF3, but then it cannot be move from IF3 to C28x memory by DMA.

    2).

    You can also try an experiment where you do not set any bit in IF3UPD but set the IF3OBS bit 2 (or any other bits) and see if you get the DMA transfer to proceed.

    The message even cannot be transfered from mailbox to IF3.

    Now, I am very anxious to confirm how to use IF3OBS bits[4:0] in DMA mode.

         Thanks!

  • Lei,

    Let me dig into IF3OBS further.  This may take me a while.

    Regards,

    Joseph

  • Hi,

       Is there any news?

  • Hi Lei,

    Sorry for the delay.  Design team is running some simulations for me but have not heard any news yet.

    Regards,

    Joseph

  • Hi,

        Is there any news?

       Regards,

        lei li

  • Hi Lei,

    Yes, just got inputs from design and they have clarified the behavior of IF3OBS.

        - The main purpose of IF3OBS register is to control the NEXT IF3 update, meaning the action from the IF3OBS setting will only take effect on the next received frame.

        Here are two examples to illustrate this:

        Example 1:

                - IF3OBS set to '2' (IF3ARB register has to be read for next IF3 update)

                - IF3UPD = '1' for mailbox 1

                - Receives first transaction and C28x RAM and IF3 are both updated

                - DMA is triggered and DMA is configured to read IF3ARB register

                - When next frame is received, both C28x RAM and IF3 registers are updated with fresh data.  IF3 DMA line is also triggered.

        Example 2:

                - IF3OBS set to 1 (IF3MSK register has to be read for next IF3 update)

                - IF3UPD = '1' for mailbox 1

                - Receives first transaction and C28x RAM and IF3 are both updated

                - DMA is triggered and DMA is configured to read IF3ARB register

                - When next frame is received, C28x RAM is updated with fresh data but IF3 registers are not updated because DMA has not read the IF3MSK register which was set in IF3OBS.  In this example IF3OBS register setting is blocking IF3 update because IF3MSK read did not happen.

    Hope the above examples illustrate the function of IF3OBS register.

    Regards,

    Joseph