TMS320F28377D: Problem of McBSP module

Dear team:

One of my customers uses McBSP modules for board-to-board communication. He wants to achieve the following functions:

Board A sends data, board B receives data, board B sends the data back to board A after receiving the data, and finally board A verifies whether the received data is consistent with the data it sent.

His project refers to the official self-loopback routine. The following is the official self-loopback routine module initialization program:

    McbspaRegs.SPCR2.all=0x0000;        // Reset FS generator, sample rate
                                        // generator & transmitter
    McbspaRegs.SPCR1.all=0x0000;        // Reset Receiver, Right justify word
    McbspaRegs.SPCR1.bit.DLB = 1;       // Enable DLB mode. Comment out for
                                        // non-DLB mode.

    McbspaRegs.RCR2.bit.RDATDLY = 1;    // RX data delay is 1 bit
    McbspaRegs.XCR2.bit.XDATDLY = 1;    // TX data delay is 1 bit

    McbspaRegs.SRGR2.bit.GSYNC = 0;     // No clock sync for CLKG
    McbspaRegs.SRGR2.bit.FPER = 320;    // Frame-synchronization period

    McbspaRegs.SRGR2.bit.FSGM = 1;      // Frame-synchronization pulses from
                                        // the sample rate generator

    McbspaRegs.SRGR2.bit.CLKSM = 1;     // Sample rate generator input clock
                                        // is LSPCLK
    McbspaRegs.PCR.bit.SCLKME = 0;

    McbspaRegs.SRGR1.bit.CLKGDV = 1;    // Divide-down value for CLKG
    delay_loop();
    McbspaRegs.SRGR1.bit.FWID = 1;      // Frame-synchronization pulse width

    McbspaRegs.PCR.bit.CLKXM = 1;       // CLKX generated internally, CLKR
                                        // derived from an external source
    McbspaRegs.PCR.bit.FSXM = 1;        // FSX generated internally, FSR
                                        // derived from an external source

    //
    // Initialize McBSP Data Length
    //
    if(data_size == 8)                  // Run a loopback test in 8-bit mode
    {
      InitMcbspa8bit();
    }
    if(data_size == 16)                 // Run a loopback test in 16-bit mode
    {
      InitMcbspa16bit();
    }
    if(data_size == 32)                 // Run a loopback test in 32-bit mode
    {
      InitMcbspa32bit();
    }

    //
    // Enable Sample rate generator and
    // wait at least 2 CLKG clock cycles
    //
    McbspaRegs.SPCR2.bit.GRST = 1;
    delay_loop();

    //
    // Release from reset
    // RX, TX and frame sync generator
    //
    McbspaRegs.SPCR2.bit.XRST = 1;
    McbspaRegs.SPCR1.bit.RRST = 1;
    McbspaRegs.SPCR2.bit.FRST = 1;

He only changed two places:

McbspaRegs.SPCR1.bit.DLB = 0; 

McbspaRegs.SRGR2.bit.FSGM = 0;

After the change, it was found that the data transmitted between the two boards were all wrong and irregular.

The initialization of the MCbsp module of the two development boards is the same. The following is the sending and receiving program in board A:

while(McbspaRegs.SPCR2.bit.XRDY == 0 ) { }

McbspaRegs.DXR1.all=txdata1A;

while(McbspaRegs.SPCR1.bit.RRDY == 0 ) { } // Check for receive

rdata1A= McbspaRegs.DRR1.all;

The following is the sending and receiving program in board B:

while(McbspbRegs.SPCR1.bit.RRDY == 0 ) { } // Check for receive
rdata1B= McbspbRegs.DRR1.all;

while(McbspbRegs.SPCR2.bit.XRDY == 0 ) { }  

txData1B=rdata1B;

McbspbRegs.DXR1.all=txdata1A;

Is there any problem with the configuration?

Best regards