Part Number: TMS320F28035
Hi expert,
I have a customer which is developing a Buck using peak current mode control.
and they use a DC input as the analog sample, to compare with internal RAMP.
however, when they increase ramp max value. and they hope the duty is near 100%, they will meet lost PWM waveform.
just as below picture
input 1 is normal, input 2 is lost PWM.
the code is attached.
it seems the comparator works, but after that the PWM is not return to high voltage for some period.
void InitePWM(void)
{
InitEPwmSyncGpio();
InitEPwmGpio();
EALLOW;
SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 0;
//EDIS;
EPwm1Regs.TBPRD = 300; // Period = 60M/200K
EPwm1Regs.TBPHS.half.TBPHS = 0;
EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; // Asymmetrical mode
EPwm1Regs.TBCTL.bit.PHSEN = TB_ENABLE;//TB_DISABLE; // slave module
EPwm1Regs.TBCTL.bit.PRDLD = TB_SHADOW;
EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;//TB_CTR_ZERO; // Sync down-stream module
EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;
EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1;
EPwm1Regs.TBCTL.bit.FREE_SOFT = 3; // free run
EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; // load on CTR=Zero
EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
EPwm1Regs.AQCTLA.bit.ZRO = AQ_SET; // set actions for EPWM1A
EPwm1Regs.DCTRIPSEL.bit.DCAHCOMPSEL = DC_COMP2OUT;
EPwm1Regs.TZDCSEL.bit.DCAEVT2 = TZ_DCAH_HI;
EPwm1Regs.DCACTL.bit.EVT2SRCSEL = DC_EVT2;
EPwm1Regs.DCACTL.bit.EVT2FRCSYNCSEL = DC_EVT_ASYNC;
EPwm1Regs.TZSEL.bit.DCAEVT2 = 1; // A force EPWMA/ B force EPMWB
EPwm1Regs.TZCTL.bit.TZA = TZ_FORCE_LO; // force A to Low
EPwm2Regs.TBPRD = 300; // Period = 60M/200K
EPwm2Regs.TBPHS.half.TBPHS = 150;
EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; // Asymmetrical mode
EPwm2Regs.TBCTL.bit.PHSEN = TB_ENABLE; // slave module
EPwm2Regs.TBCTL.bit.PRDLD = TB_SHADOW;
EPwm2Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; // Sync down-stream module
EPwm2Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;
EPwm2Regs.TBCTL.bit.CLKDIV = TB_DIV1;
EPwm2Regs.TBCTL.bit.FREE_SOFT = 3; // free run
EPwm2Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
EPwm2Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm2Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; // load on CTR=Zero
EPwm2Regs.AQCTLA.bit.ZRO = AQ_SET; // set actions for EPWM1A
EPwm2Regs.DCTRIPSEL.bit.DCAHCOMPSEL = DC_COMP3OUT;
EPwm2Regs.TZDCSEL.bit.DCAEVT2 = TZ_DCAH_HI;
EPwm2Regs.DCACTL.bit.EVT2SRCSEL = DC_EVT2;
EPwm2Regs.DCACTL.bit.EVT2FRCSYNCSEL = DC_EVT_ASYNC;
EPwm2Regs.TZSEL.bit.DCAEVT2 = 1; // A force EPWMA/ B force EPMWB
EPwm2Regs.TZCTL.bit.TZA = TZ_FORCE_LO; // force A to Low
EPwm2Regs.HRPCTL.bit.PWMSYNCSEL = 1;
EPwm3Regs.TBPRD = 300; // Period = 60M/100K
EPwm3Regs.TBPHS.half.TBPHS = 0;
EPwm3Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Symmetrical mode
EPwm3Regs.TBCTL.bit.PHSEN = TB_ENABLE; // slave module
EPwm3Regs.TBCTL.bit.PRDLD = TB_SHADOW;
EPwm3Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; // sync flow-through
EPwm3Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;
EPwm3Regs.TBCTL.bit.CLKDIV = TB_DIV1;
EPwm3Regs.TBCTL.bit.FREE_SOFT = 3; // free run
EPwm3Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
EPwm3Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm3Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; // load on CTR=Zero
EPwm3Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
// interrupt
EPwm3Regs.ETSEL.bit.INTSEL = 1; // Select INT on 0 event
EPwm3Regs.ETSEL.bit.INTEN = 1; // Enable INT
// EPwm3Regs.ETSEL.bit.SOCAEN = 1;
EPwm3Regs.ETPS.bit.INTPRD = 1; // Generate INT on 1st event
//EALLOW;
SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC=1;
EPwm1Regs.TBCTL.bit.SWFSYNC = 1; // Synchronize high resolution phase to start HR period
EPwm2Regs.TBCTL.bit.SWFSYNC = 1;
EPwm3Regs.TBCTL.bit.SWFSYNC = 1;
EDIS;
}
void InitComparator(void)
{
EALLOW;
// Vin protect
Comp1Regs.COMPCTL.bit.SYNCSEL = 0; // asy
Comp1Regs.COMPCTL.bit.QUALSEL = 12; // 200ns=16.66667*12
Comp1Regs.COMPCTL.bit.CMPINV = 0;
Comp1Regs.COMPCTL.bit.COMPSOURCE= 0;
Comp1Regs.COMPCTL.bit.COMPDACEN = 1;
Comp1Regs.DACCTL.bit.FREE_SOFT = 3;
Comp1Regs.DACCTL.bit.RAMPSOURCE = 0;
Comp1Regs.DACCTL.bit.DACSOURCE = 0; // da value
AdcRegs.COMPHYSTCTL.bit.COMP1_HYST_DISABLE = 1;
// Is1 PCM
Comp2Regs.COMPCTL.bit.SYNCSEL = 0;
Comp2Regs.COMPCTL.bit.QUALSEL = 12; // 200ns=16.66667*12
Comp2Regs.COMPCTL.bit.CMPINV = 0;
Comp2Regs.COMPCTL.bit.COMPSOURCE= 0;
Comp2Regs.COMPCTL.bit.COMPDACEN = 1;
Comp2Regs.DACCTL.bit.FREE_SOFT = 3;
Comp2Regs.DACCTL.bit.RAMPSOURCE = 0;
Comp2Regs.DACCTL.bit.DACSOURCE = 1; // ramp
Comp2Regs.RAMPDECVAL_SHDW = 22;
Comp2Regs.RAMPMAXREF_SHDW = 86*64; // da*64
AdcRegs.COMPHYSTCTL.bit.COMP2_HYST_DISABLE = 1;
// Is2 PCM
Comp3Regs.COMPCTL.bit.SYNCSEL = 0;
Comp3Regs.COMPCTL.bit.QUALSEL = 12; // 200ns=16.66667*12
Comp3Regs.COMPCTL.bit.CMPINV = 0;
Comp3Regs.COMPCTL.bit.COMPSOURCE= 0;
Comp3Regs.COMPCTL.bit.COMPDACEN = 1;
Comp3Regs.DACCTL.bit.FREE_SOFT = 3;
Comp3Regs.DACCTL.bit.RAMPSOURCE = 0;
Comp3Regs.DACCTL.bit.DACSOURCE = 1; // ramp
Comp3Regs.RAMPDECVAL_SHDW = 22;
Comp3Regs.RAMPMAXREF_SHDW = 86*64;
// AdcRegs.COMPHYSTCTL.bit.COMP3_HYST_DISABLE = 1;
EDIS;
}
could you kindly point out the possible wrong setting?
BR
Emma
