TMS320F28034: The specific process of nesting interrupt

Johnny Chen

Part Number: TMS320F28034
Other Parts Discussed in Thread: C2000WARE

Hi Champ,

I am asking for my customers.

They are using the nesting interrupt in their program.

By doing EWPM5_INT could interrupt ADC1_INT, so the total time of ADC1_INT been nesting interrupted = routine time of ADC1_INT + time of EWPM5_INT + extra time delay(6us).

They would want to know where does the extra time delay come from ?

May I know specific process of nesting interrupt that I think it might cause the extra time delay ? Am I correct ?

It would be perfect if there is a figure of explaining the process.

Thanks

BR, Johnny

over 4 years ago

0 Whitney Dewey over 4 years ago

TI__Guru 54195 points

Hi Johnny,

You can take a look at the sw_prioritized_interrupts example in C2000Ware to see the code that needs to be executed to next interrupts. To give you a sample ISR though, I'll past some code here:

__interrupt void 
ADCINT1_ISR( void )
{
    //
    // Set interrupt priority:
    //
    volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER1.all;
    
    IER |= M_INT1;
    IER	&= MINT1;	  	               // Set "global" priority
    PieCtrlRegs.PIEIER1.all &= MG11;   // Set "group"  priority
    PieCtrlRegs.PIEACK.all = 0xFFFF;   // Enable PIE interrupts
    __asm("  NOP");
    EINT;

    //
    // Insert ISR Code here
    //
    for(i = 1; i <= 10; i++)
    {
        
    }

    //
    // Restore registers saved
    //
    DINT;
    PieCtrlRegs.PIEIER1.all = TempPIEIER;

    //
    //  Add ISR to Trace
    //
    ISRTrace[ISRTraceIndex] = 0x0011;
    ISRTraceIndex++;
}

You can ignore the ISRTrace stuff and the for loop--those are just there to show how the example works. The main thing enabling the nesting is the masking of different bits in IER and PIEIERx, clearing the PIEACK, reenabling interrupts, and then restoring the value of PIEIERx in the end. Are they counting the execution of those lines already in their "time of ADC1_INT" and "time of EWPM5_INT" numbers?

Some of that extra time is related to the context save and restore of the nested interrupt although not the full 6 us. What is their SYSCLK speed? 60 MHz?

How are they measuring the execution time? Toggling GPIOs?

Whitney

0 Johnny Chen over 4 years ago in reply to Whitney Dewey

TI__Expert 5080 points

Hi Whitney,

Thanks for showing me how to implement the nesting interrupt. I have supported the customer to implement nesting interrupt successfully.

You are correct. The extra time delay is actually 5.75 us, not the full 6 us and measured by toggling GPIOs on the oscilloscope. (SYSCLK

speed is 60M Hz) How do you know that it is not the full 6 us, may I know ?

If there are only two ISR (EWPM5_INT and ADC1_INT) in the program, could I firmly tell the extra time delay comes from the context save and

restore of the nested interrupt ? Could I make sure of this ?

Also, do we have any specific document shows the latency of the context save and restore of the nested interrupt ? This is what I want to know.

Thanks !

BR, Johnny

0 Whitney Dewey over 4 years ago in reply to Johnny Chen

TI__Guru 54195 points

Are you toggling GPIOs in both ISRs? Can you give me more details like how long does it take for each ISR to execute on its own when nesting doesn't occur?

Minimum interrupt latency is around 14 cycles. I couldn't find the return/restore documented, but I think it's around 10. The latency could be more considering wait states, whether or not interrupts are disabled by the application at any point, etc...

I think the device workshops have a nice description of the interrupt latency although it doesn't specifically cover nesting:

https://dev.ti.com/tirex/explore/node?node=AO3tuUWy1t1n-PFt5oLFCQ__jEBbtmC__LATEST

There's a doc on nesting here although it doesn't talk about cycle counts:

https://software-dl.ti.com/C2000/docs/c28x_interrupt_nesting/html/index.html

Whitney

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TMS320F28034: The specific process of nesting interrupt