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TMS320F28379D: Calculation of fast current loop time in FCL evaluation project

Green Deng
Expert 4490 points

Part Number: TMS320F28379D
Other Parts Discussed in Thread: TMDXIDDK379D, C2000WARE

Dear team:

My clients has some doubts about the following questions:

In the routine: C:\ti\c2000\C2000Ware_MotorControl_SDK_3_02_00_00\solutions\tmdxiddk379d\f2837x

When using LEM_CURRENT_SENSE current sampling, the current loop interrupt is triggered by the timer of EPWM1, namely: INT_EPWM1=>&motorControlISR;

When using SD_CURRENT_SENSE current sampling, the current loop interrupt is triggered by the timer of EPWM11: INT_EPWM11=> &motorControlISR;

The "fclLatencyInMicroSec" in the project is calculated by the counter of EPWM1, and the interrupt time of INTEPWM1 and INT_EPWM11 are different.

Therefore, in SD_CURRENT_SENSE mode, it is necessary to change the reading method to differential mode. It is read once when entering interrupt and once out of current loop. Is this more reasonable?

Best regards

  • 0
    TI__Mastermind 27240 points

    No, the intent is to capture the time it takes to complete updating U, V W compare registers from the PRD or ZRO event. Hope it is clear.

  • 0 in reply to Ramesh Ramamoorthy
    TI__Expert 4490 points

    Hi Ramesh:

    Customer feedback, this is a problem found when comparing the current sampling methods.
    It is correct in LEM_CURRENT_SENSE mode, and the time consumption is about 0.98us.
    In SD_CURRENT_SENSE mode, it is 15.67us, which is a big difference.

    By reading the EPWM CTR count value at the beginning of the __interrupt void motorControlISR(void) program, it is found that in SD_CURRENT_SENSE mode, the value at this time has reached about 1482.
    After updating the U, V, and W comparison registers, read the EPWM CTR count value again, which is about 1600, and the difference between the two is 118, which is converted into a time of 1.18us, which is in line with expectations. The sample code directly presses EPWM CTR =0 as the starting point for the timing is 15.67us.

    The state quantity fclLatencyInMicroSec is correct in the LEM_CURRENT_SENSE mode. This time consumption in the SD_CURRENT_SENSE mode is ambiguous and needs to be corrected. This timing deviation does not affect the execution efficiency.

    Best regards

  • 0 in reply to Green Deng
    TI__Mastermind 27240 points

    Green,

    With SAR ADC, the EPWM ISR is and ADC are both triggered by the same event  (ZRO or PRD). Within the ISR, we wait for ADC EOC before reading the result register.

    With SDFM, we link EPWM11 to reset the SDFM data and restart bit accumulation N/2 cycles ahead of ZRO or PRD event. It will take another N/2 cycles post ZRO or PRD event for the result to be available. We give some addition margin to ensure that we read the value after it is available and hence it takes a little more time. With a OSR of, say, 100, and with sync 3 filter, N will be equal to 3*100 = 300 clocks. At 20 MHz clock, N/2 samples from ZRO or PRD event will mean 7.5us. I just picked a number for discussion sake. Nevertheless, it is an inherent issue with SD filter.