• State Resolved
  • Locked Locked
  • Replies 3 replies
  • Subscribers 83 subscribers
  • Views 710 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TMS320F28388D: GPIO behavior with slow digital input signals

Sebastian Ausserwoeger
Prodigy 230 points

Part Number: TMS320F28388D

Hi,

we're planning to use the F28388D in one of our next electronics designs. This upcoming design has lots of digital inputs coming from open collector circuits with pull-ups & RC-filtering and thus typically have quite slow rise and fall times in the range of a few 10µs.

I have already checked the F28388D's datasheet regarding potential limitations on transition rates (as is the case for the good old SN74HC CMOS logic family for example) - but couldn't find any. On the contrary - I was pleasantly surprised that all GPIOs seem to have a 150mV input hysteresis, as stated in datasheet section 7.6 - so I assume oscillations are not an issue.

Now, we wan't to be sure that we do not run into potential problems here, so my question is if there are any known issues regarding the F28388D's GPIO input structure in combination with slow input signals that might lead to an undesired device behavior or even damage the device (e.g. due to high shoot-trough currents in the GPIO's input buffer).

I want to point out that my question is not related to any communication, memory interfaces or similar where timing is essential of course. This is rather about "uncritical" input signals (e.g. momentary switches).

Appreciate your feedback. Thanks.

Best regards,

Sebastian

  • 0
    TI__Guru 52200 points
    Sebastian Ausserwoeger said:
    I was pleasantly surprised that all GPIOs seem to have a 150mV input hysteresis, as stated in datasheet section 7.6 - so I assume oscillations are not an issue.

    Yes we have Hysteresis.

    You will have leakage current. I think you are fine however.

    do you see any issue with slow signals that rise from 0 to 1 in approx 10us?

    Nima

  • +1
    TI__Expert 6010 points

    Nima, Sebastian,

    That is correct, there should be no issue with slow rising signals causing damage to the device.  There will be a small increased VDDIO current as the signal passes through the mid-band but as long as ultra-low power is not a critical parameter then this is not an issue.

    One additional feature we have for signals like this on F28x devices is the GPIO input qualification logic.  You can use this to do some nice digital filtering on top of the analog hysteresis of the input buffer for de-bounce applications.  Check out the TRM GPIO chapter for details here.

    Best regards,

    Jason

  • 0 in reply to Jason Whiles
    Prodigy 230 points

    Hi Nima and Jason,

    that's why I love this community. Quick and helpful response. Thank you - appreciate you work.

    Best regards,

    Sebastian