In my board after pll and osc configuration (external crystal osc), configuration made like TI example, I see PLLSTS.PLLOFF bit set.
I never set this bit and the board seem work correctly. What mean this bit?...PLL is OFF?
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In my board after pll and osc configuration (external crystal osc), configuration made like TI example, I see PLLSTS.PLLOFF bit set.
I never set this bit and the board seem work correctly. What mean this bit?...PLL is OFF?
That bit is doing exactly what it says. The PLL is used to get higher frequency clocks than the internal oscillator clocks. If it is off you are basically getting the oscillator clock straight into SYSCLK, which means the board will work correctly, all be it slower than possible. It is all summed up on pages 40-43 of: http://focus.ti.com/lit/ug/sprufb0d/sprufb0d.pdf
Tim