Part Number: TMS320F28379D
Hello,
I stumbled upon compiler error for Delfino F28379D compiler (checked on TI compilers 20.2.1 and 21.6.0).
Below minimal code example to invoke compiler error:
#include <stddef.h>
#include <stdlib.h>
typedef struct
{
float a; float b;
float c; float d;
float e; float f;
float in; float in_prev;
} str;
typedef struct
{
float reserved[25];
str aa;
} movd32_example;
#pragma DATA_ALIGN ( md32 , 0x40 )
movd32_example md32;
static inline void calculate(str *a, float in) {
a->c = a->a * a->in_prev + a->b * a->c;
a->in_prev = in;
a->e = a->f * (a->in - a->c);
a->d = in - a->e;
}
void main(void) {
for (;;) {
md32.aa.in = (rand() % 100) / 10.0f;
calculate(&md32.aa, md32.aa.in);
}
}
For my project (attached), linker places m32 at address 0xa800 - at the beginning of 64 word page.
Line
a->in_prev = in;
is realised as following set of instructions:
MOVW DP,#_md32+64 ; [CPU_ARAU] MOV32 *+XAR4[AR1],R0H ; [CPU_FPU] |30| MOVB XAR1,#58 ; [CPU_ALU] |24| MOV32 R2H,*+XAR4[AR0] ; [CPU_FPU] |24| SUBF32 R1H,R2H,R1H ; [CPU_FPU] |24| MOVD32 R4H,@$BLOCKED(_md32)+62 ; [CPU_FPU] |23|
Last MOVD32 instruction uses direct addressing, so DP register needs to be set for data page number, and in MOVD32 instruction, only last 6 bits are passed.
Intended effect of MOVD32 instruction is:
R4H := [md32+62:md32+63]
[md32+64:md32+65] := [md32+62:md32+63]
due to md32+62 and md32+64 addresses being on different 64 word pages, and DP register set to md32+64 page, both parts of movd32 instruction are executed incorrectly.
R2H register gets value from md32+126 instead of md32+62, and this value is written to md+128, potentially overwriting some other data.
I attach compete CCS project to reproduce this fenomenon.
