TMS320F28379D: Different Behavior Between Identically Configured ePWM Modules on Core 2

Owen, All ePWM assigned to CPU2?

All configuration done on CPU2 for the EPWM regs?

What is the difference between EPWM1-6 configs and EPWM7-12?

Nima, all ePWMs are assigned to CPU2. In pulling all the config information together into one function (shown above) the fact that CPU1 is running lines 4-12 was lost. In my actual program, CPU1 delegates all the ePWM modules to CPU2 and sets the GPIO configurations. 

The ePWM module configuration all happens on CPU2. There should be no difference between any of the ePWM configs - they all use the exact same code as shown above (in my project, it's parameterized so I can just pass in a different base address). 

Here is the actual init_pwm() function from my project:

void init_epwm(uint32_t base, bool ie)
{
	// Set-up TBCLK
	EPWM_setTimeBasePeriod(base, EPWM_TIMER_TBPRD);
	EPWM_setPhaseShift(base, 0U);
	EPWM_setTimeBaseCounter(base, 0U);
	EPWM_disableInterrupt(base);

	// Set Compare values
	EPWM_setCounterCompareValue(base, EPWM_COUNTER_COMPARE_A, 0U);
	EPWM_setCounterCompareValue(base, EPWM_COUNTER_COMPARE_B, 0U);

	// Set up counter mode
	EPWM_setTimeBaseCounterMode(base, EPWM_COUNTER_MODE_UP_DOWN);//EPWM_COUNTER_MODE_UP);
	EPWM_disablePhaseShiftLoad(base);
	EPWM_setClockPrescaler(base, EPWM_CLOCK_DIVIDER_1, EPWM_HSCLOCK_DIVIDER_1);

	// Set up shadowing
	EPWM_setCounterCompareShadowLoadMode(base, EPWM_COUNTER_COMPARE_A, EPWM_COMP_LOAD_ON_CNTR_ZERO);
	EPWM_setCounterCompareShadowLoadMode(base, EPWM_COUNTER_COMPARE_B, EPWM_COMP_LOAD_ON_CNTR_ZERO);

	// Set actions - PWM A/B are configured to be inverse from one another, based on the CMPA register
	EPWM_setActionQualifierAction(base,
											EPWM_AQ_OUTPUT_A,
											EPWM_AQ_OUTPUT_LOW,
											EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA);
	EPWM_setActionQualifierAction(base,
											EPWM_AQ_OUTPUT_A,
											EPWM_AQ_OUTPUT_HIGH,
											EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPA);


	EPWM_setActionQualifierAction(base,
											EPWM_AQ_OUTPUT_B,
											EPWM_AQ_OUTPUT_HIGH,
											EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPB);
	EPWM_setActionQualifierAction(base,
											EPWM_AQ_OUTPUT_B,
											EPWM_AQ_OUTPUT_LOW,
											EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPB);

	// Select INT on Time base counter zero event,
	// Enable INT, generate INT on Nth event
	if(ie)
	{
		EPWM_setInterruptSource(base, EPWM_INT_TBCTR_ZERO);
		EPWM_enableInterrupt(base);
		EPWM_setInterruptEventCount(base, EPWM_ISR_EVENT_COUNT);
	}
}

Here is a code snippet showing how the PWMs are delegated to their respective motor groups:

	switch (m_num)
	{
	case M1:
		pwm1_base = EPWM12_BASE;
		pwm2_base = EPWM11_BASE;
		pwm3_base = EPWM8_BASE;
		break;
	case M2:
		pwm1_base = EPWM7_BASE;
		pwm2_base = EPWM10_BASE;
		pwm3_base = EPWM9_BASE;
		break;
	case M3:
		pwm1_base = EPWM6_BASE;
		pwm2_base = EPWM5_BASE;
		pwm3_base = EPWM2_BASE;
		break;
	case M4:
		pwm1_base = EPWM4_BASE;
		pwm2_base = EPWM3_BASE;
		pwm3_base = EPWM1_BASE;
		break;

	}

Here is a code snippet showing when the init_epwm() function is called (for M1, M2, M3, and M4 separately).

SysCtl_disablePeripheral(SYSCTL_PERIPH_CLK_TBCLKSYNC);

	init_epwm(pwm1_base, true); // ie only for first PWM in group
	init_epwm(pwm2_base, false);
	init_epwm(pwm3_base, false);


	switch (m_num)
	{
		case M1:
				Interrupt_register(INT_EPWM12, &m1_pwm_isr)
				Interrupt_enable(INT_EPWM12);
				break;
		case M2:
				Interrupt_register(INT_EPWM7, &m2_pwm_isr);
				Interrupt_enable(INT_EPWM7);
				break;
		case M3:
				Interrupt_register(INT_EPWM6, &m3_pwm_isr);
				Interrupt_enable(INT_EPWM6);
				break;
		case M4:
				Interrupt_register(INT_EPWM4, &m4_pwm_isr);
				Interrupt_enable(INT_EPWM4);
				break;
	}

Here are the ISRs for each of the 4 PWM interrupts:

__interrupt void m1_pwm_isr(void)
{
    m1_tick();
	// Clear INT flag for this timer
	EPWM_clearEventTriggerInterruptFlag(EPWM12_BASE);

	// Acknowledge interrupt group
	Interrupt_clearACKGroup(INTERRUPT_ACK_GROUP3);
}

__interrupt void m2_pwm_isr(void)
{
    m2_tick();
	// Clear INT flag for this timer
	EPWM_clearEventTriggerInterruptFlag(EPWM7_BASE);

	// Acknowledge interrupt group
	Interrupt_clearACKGroup(INTERRUPT_ACK_GROUP3);
}

__interrupt void m3_pwm_isr(void)
{
    m3_tick();
	// Clear INT flag for this timer
	EPWM_clearEventTriggerInterruptFlag(EPWM6_BASE);

	// Acknowledge interrupt group
	Interrupt_clearACKGroup(INTERRUPT_ACK_GROUP3);
}

__interrupt void m4_pwm_isr(void)
{
    m4_tick();
	// Clear INT flag for this timer
	EPWM_clearEventTriggerInterruptFlag(EPWM4_BASE);

	// Acknowledge interrupt group
	Interrupt_clearACKGroup(INTERRUPT_ACK_GROUP3);
}

It should be noted that there are no issues with the ePWM modules associated with M1 and M2 - just M3 and M4 (PWM<1-6>) don't seem to work (the output doesn't switch, but is driven). 

Nima, all of the PWM modules work in a separate test project. My issue was not with PWM configuration, but with my PWM ISR taking too long which was not updating the PWMs associated with M3 and M4 (coincidentally PWM<1-6>). The issue has been resolved.

Thanks again!