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TMS320F28075: Dual Motor FCL: Single vs Double Sampling ePWM Offsets

Part Number: TMS320F28075


I recently changed from working with the Double Sampling Configuration to Single Sampling using the Dual Motor FCL Projects.  When using double sampling the M1 and M2 ISRs were offset by 1/2 a Period.  I.e. If running at 10 Khz (100 us) each ISR was 50 uS apart from each other.  After I switched from  Double -> Single, I see that the M2 waveform is shifted by 1/4 of a period instead of 1/2.  This behavior is causing some timing issues with other parts of our system.

I believe that the following code from HAL_setupMotorPWMs is responsible for synchronizing the time base between the two motors:

    else if(handle == &halMtr[MTR_2])
        halfPeriod = M2_INV_PWM_TICKS/2;     // 100MHz EPWMCLK

        EPWM_setPhaseShift(obj->pwmHandle[0], ((halfPeriod>>1) + 0));
        EPWM_setPhaseShift(obj->pwmHandle[1], ((halfPeriod>>1) + 2));
        EPWM_setPhaseShift(obj->pwmHandle[2], ((halfPeriod>>1) + 4));

        EPWM_setTimeBasePeriod(obj->pwmHandle[0], halfPeriod);
        EPWM_setTimeBasePeriod(obj->pwmHandle[1], halfPeriod);
        EPWM_setTimeBasePeriod(obj->pwmHandle[2], halfPeriod);


  1. When running in Single Sampling mode, is there any reason that the period is divided by two again?  When I remove the ">>1" the setPhaseShift the motor draws a lot of current and doesn't rotate (as if Id is really high).  However, when I look at the ISR timing on a scope, they are evenly split across the PWM period.
  2. While I was trying to root cause this behavior, I noticed that the carrierMid value is scaled differently for Dual and Single Sampling Setups.  (initMotorParameters function in dual_axis_servo_drive_user.c) Is this intentional?
            pMotor->maxModIndex = (M1_TPWM_CARRIER -
                    (2 * M1_FCL_COMPUTATION_TIME)) / M1_TPWM_CARRIER;
            pMotor->FCL_params.carrierMid = pMotor->maxModIndex *
                    M1_INV_PWM_HALF_TBPRD * 0x10000L;
            pMotor->maxModIndex = (M1_TPWM_CARRIER -
                    (4 * M1_FCL_COMPUTATION_TIME)) / M1_TPWM_CARRIER;
            pMotor->FCL_params.carrierMid = M1_INV_PWM_HALF_TBPRD * 0x10000L;



  • 1. The intent is to spread the sampling across 100us as follows:

    AT 0us and 50 us, the ISR will correspond to M1, and at 25us and 75us --> M2.To achieve this, the phase shift values are moved by 180 degrees wrt each motor. Did you run into any performance issue with DOUBLE_SAMPLING?

    2. Yes, with SINGLE sampling, we can move the common mode point down a little bit (or, up depending on ZRO event or PRD event triggering this ISR) so as to get a higher modulation index that keeping it at 50%

  • Hi Ramesh,

    I changed from double to single sampling since I was increasing the PWM duty cycle form 10->20 Khz to remove an audible whine on our motors.  By reducing the ISR rate by half while doubling the PWM I was able to keep the CPU loading the same. While i'm sure that the FCL loop can run at 20 khz Double Sampling, we have other requirements the system needs to accomplish.

    1. For single sampling at 20 Khz, I was seeing M1 ISR at 0, and 50 us.  I was seeing M2 ISR at 37.5 us and 87.5 us.  This is because the ((halfPeriod>>1) actually shifts the pwm duty cycle by 1/4 of the triangle period. 

    I presume the +2, and +4 on the phase shift are to remove EMI.  I realized that my issue with just removing (>> 1) really changes the phase shift to half_period +2 half period +4.  In the single sampling use case, half period + anything shifts M2 PWM higher than the PRD and results in the PRD compare never happening.  I.e. why one motor was just stuck.  Imagine high Id and 0 Iq. 

    2. Can you explain this a bit more for me?  Why would it be different if we were sampling on Zero and PRD? 

    3. We have an internal company debate about sampling time.  We currently sample current on PWM Zero.  In this use case I believe all low side FETs are ON and all high side FETS are off.  I.e. low side Null Vector.

    Our EEs want to put low pass (rc) filters on the current sensing.  They would put the cut off frequency higher than the max electrical frequency that we would expect. Their theory is that the control loop should operate on the average current seen by the motor phase and that a low pass filter will average out the inverter noise and current ripple.  I'm concerned about phase delay and unnecessarily reducing the current loop bandwidth.

    Should you put a low pass filter into the design to remove the switching frequency?



  • There could be some mistake in our code. The intent is to split the ISR instances in equal time period and the second motor's carrier should be shifted accordingly. You can try figuring it by sliding the phase shift of the second carrier wrt the first so that the ISRs timing spread out equally.

    2. We lose some time for comp right after sampling. With single sampling, this happens close to either ZRO or PRD. This leads to unsymmetric time loss. Hence you can move the mid point of carrier accordingly instead of keeping it at 50% to make full use of the available room. This will lead to gaining a few % points on modulation index depending on the carrier frequency.

     3. Using LPF on sensed current should be to filter frequencies above switching frequency, and not switching frequency itself as the current signature is embedded in the ripple at the switching frequency. You need to recover the actual shape of the current pulse in the shunt resistor and sample it at the middle of PWM pulse.