TMS320F280025C: Problem to configure CMPSS on TMS320f280025C

Hi Damien,

Welcome to the e2e forum. Will be glad to help you resolve your issue. I didn't quite understand your issue below. Can you explain a little more what doesn't work?

DAMIEN CHARNAY said:

It work correctly when i use only two ADCIN : only with XBAR_MUX00 and XBAR_MUX02 but not with another.

Hi Franck,

I use the ADC inputs that are connected to the CMP1_HP signals for example, I set the DAC to a certain threshold and I use an external power supply that fits on the ADC inputs for the simulation. The objective  will of course be to link OCP/OVP feedbacks to these inputs. I use the pin allocation table to link the ADC entry to the CMPSS in question. If I understand correctly I can assign several CMPSS to the same signal of the trip zone (XBAR_TRIP4) ? Can I connect multiple multiplexers to the same trip zone cutt-off signals (XBAR_TRIP4) ?

When I use this config it work correctly (Shut-down Ok) :

XBAR_setEPWMMuxConfig(XBAR_TRIP4, XBAR_EPWM_MUX00_CMPSS1_CTRIPH);
XBAR_setEPWMMuxConfig(XBAR_TRIP4, XBAR_EPWM_MUX02_CMPSS2_CTRIPH);

XBAR_enableEPWMMux(XBAR_TRIP4, XBAR_MUX00, XBAR_MUX02);

But when I want to add another CMPSS with antoher ADC entry it doesn't work ? Using the same trip zone or antoher. For example this code doesn't work for the MUX06:

XBAR_setEPWMMuxConfig(XBAR_TRIP4, XBAR_EPWM_MUX00_CMPSS1_CTRIPH);
XBAR_setEPWMMuxConfig(XBAR_TRIP4, XBAR_EPWM_MUX02_CMPSS2_CTRIPH);
XBAR_setEPWMMuxConfig(XBAR_TRIP4, XBAR_EPWM_MUX06_CMPSS4_CTRIPH);

XBAR_enableEPWMMux(XBAR_TRIP4, XBAR_MUX00 | XBAR_MUX02 | XBAR_MUX06 );

I will see if it's a problem of configuration of the microcontrolleur, on the pin concerned I may not fit  on the CMPSS but another function (see on the table pin attributes)

Hi,

I think the problem is the CMPSS config : relation CMPx_HPx to Analog Input Output no ?

My config is here : 

float init_EPWM(base)
{
float PWM_TBPRD;
float PWM_CMPA;
EPWM_ClockDivider PWM_PARAM_PRESCALER;
EPWM_HSClockDivider PWM_PARAM_HIGHSPEEDPRESCALER;
float TBCLK;

get_pwm_clock_from_freq(&PWM_TBPRD , &PWM_CMPA , &PWM_PARAM_PRESCALER , &PWM_PARAM_HIGHSPEEDPRESCALER, &TBCLK);

// Parameters
EPWM_setTimeBasePeriod(base, (uint16_t)PWM_TBPRD);
EPWM_setCounterCompareValue(base, EPWM_COUNTER_COMPARE_A, (uint16_t)PWM_CMPA);
EPWM_setPhaseShift(base, 0U);
EPWM_setTimeBaseCounter(base, 0U);
EPWM_setTimeBaseCounterMode(base, EPWM_COUNTER_MODE_UP_DOWN);
EPWM_disablePhaseShiftLoad(base);
EPWM_setClockPrescaler(base, PWM_PARAM_PRESCALER, PWM_PARAM_HIGHSPEEDPRESCALER);

// Set up shadowing
EPWM_setCounterCompareShadowLoadMode(base, EPWM_COUNTER_COMPARE_A, EPWM_COMP_LOAD_ON_CNTR_ZERO);

// Set actions
EPWM_setActionQualifierAction(base, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_HIGH, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA);
EPWM_setActionQualifierAction(base, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_LOW, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPA);
EPWM_setActionQualifierAction(base, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_HIGH, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA);
EPWM_setActionQualifierAction(base, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_LOW, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPA);

// Trip zone
// Configure ePWM1x to output low on TZx TRIP
EPWM_setTripZoneAction(base, EPWM_TZ_ACTION_EVENT_TZA, EPWM_TZ_ACTION_LOW);
EPWM_setTripZoneAction(base, EPWM_TZ_ACTION_EVENT_TZB, EPWM_TZ_ACTION_LOW);
// Trigger event when DCBH is high
EPWM_setTripZoneDigitalCompareEventCondition(base, EPWM_TZ_DC_OUTPUT_B1, EPWM_TZ_EVENT_DCXH_HIGH);
// Configure DCBH to use TRIP4 as an input
EPWM_enableDigitalCompareTripCombinationInput(base, EPWM_DC_COMBINATIONAL_TRIPIN4, EPWM_DC_TYPE_DCBH);
// Enable DCB as OST
EPWM_enableTripZoneSignals(base, EPWM_TZ_SIGNAL_DCBEVT1);
// Configure the DCB path to be unfiltered and asynchronous
EPWM_setDigitalCompareEventSource(base, EPWM_DC_MODULE_B, EPWM_DC_EVENT_1, EPWM_DC_EVENT_SOURCE_ORIG_SIGNAL);

//AIO224 -> myAIO0 Pinmux
GPIO_setPinConfig(GPIO_224_GPIO224);
GPIO_setAnalogMode(224, GPIO_ANALOG_ENABLED);
//AIO230 -> myAIO1 Pinmux
GPIO_setPinConfig(GPIO_230_GPIO230);
GPIO_setAnalogMode(230, GPIO_ANALOG_ENABLED);
//AIO226 -> myAIO2 Pinmux
GPIO_setPinConfig(GPIO_226_GPIO226);
GPIO_setAnalogMode(226, GPIO_ANALOG_ENABLED);
// To use CMP1_HP0
ASysCtl_selectCMPHPMux(ASYSCTL_CMPHPMUX_SELECT_1, 0);
// To use CMP2_HP3
ASysCtl_selectCMPHPMux(ASYSCTL_CMPHPMUX_SELECT_2, 3);
// To use CMP3_HP0
ASysCtl_selectCMPHPMux(ASYSCTL_CMPHPMUX_SELECT_3, 0);

// Configure TRIP4 to be CTRIP1H using the ePWM X-BAR
XBAR_setEPWMMuxConfig(XBAR_TRIP4, XBAR_EPWM_MUX00_CMPSS1_CTRIPH);
XBAR_setEPWMMuxConfig(XBAR_TRIP4, XBAR_EPWM_MUX02_CMPSS2_CTRIPH);
XBAR_setEPWMMuxConfig(XBAR_TRIP4, XBAR_EPWM_MUX04_CMPSS3_CTRIPH);

// See the ePWM X-BAR Mux configuration table
XBAR_enableEPWMMux(XBAR_TRIP4, XBAR_MUX00 | XBAR_MUX02 | XBAR_MUX04);
// Clear trip flags
EPWM_clearTripZoneFlag(base, EPWM_TZ_INTERRUPT | EPWM_TZ_FLAG_OST);
return TBCLK;
}

Can you help me please ?

Thanks

Best regards

Damien

Hi,

I use CMP1_HP1 with AIO224 to pin 13 (80QFP for my µC)

         CMP2_HP3 with AIO230 to pin 29 (80QFP for my µC)

         CMP3_HP0 with AIO226 to pin 11 (80QFP for my µC)

When I apply 1V (ref DAC = 1024) with a power supply on the pins (13 and 29)  ePWMs shut down correctly but when I apply on the pin number 11 it doesn't work. Why ? Can you explain me please ?

Thanks 

Damien

Hi Damien,

Glad to hear you resolved the issue! Let us know if anymore come up.

Hi Frank,

I have a new issue about my ePWM output when I use CMPxLP inputs so CTRIPxL outputs.

When I use CMPxHP inputsto shut-down my ePWM everything work fine. (only with CMPxHP inputs and ref by DAC)

This is the configuration used in our previous exchanges. I now try to use the CMPSS in their entirety by also using the CMP_LP inputs but in this case ePWM are asynchronized. I don't understand why ? I join below code and ePWM concerned.

and the code :

#include <f28002x_device.h>
#include "driverlib.h"
#include "utils.h"
#include "device.h"
#include "board.h"
#include "config.h"

float init_EPWM();
void init_cmpss();

void main(void)
{
    // Initialize device clock and peripherals
    Device_init();
    // Disable pin locks and enable internal pullups.
    Device_initGPIO();
    // Initialize PIE and clear PIE registers. Disables CPU interrupts.
    Interrupt_initModule();
    // Initialize the PIE vector table with pointers to the shell Interrupt Service Routines (ISR).
    Interrupt_initVectorTable();
    // board.c and board.h generate by sysconfig
    Board_init();

    // Disable sync and clock to PWM
    SysCtl_disablePeripheral(SYSCTL_PERIPH_CLK_TBCLKSYNC);
    // Configure COMP1H
    init_cmpss(CMPSS1_BASE);
    init_cmpss(CMPSS2_BASE);
    init_cmpss(CMPSS3_BASE);
    // initEPWM1 - Configure ePWM1
    float tbclk = init_EPWM(myEPWM1_BASE);
    // initEPWM2 - Configure ePWM2
    tbclk = init_EPWM(myEPWM2_BASE);
    // Configure phase between PWM1 & PWM2. PWM1 is configure as master and ePWM2 as slaves.
    EPWM_disablePhaseShiftLoad(myEPWM1_BASE);
    EPWM_setPhaseShift(myEPWM1_BASE, 0U);
    // ePWM1 SYNCO is generated on CTR=0
    EPWM_enableSyncOutPulseSource(myEPWM1_BASE, EPWM_SYNC_OUT_PULSE_ON_CNTR_ZERO);

    // Configure phase shift for EPWM2 & 3
    set_phase(myEPWM2_BASE, PHI);
    EPWM_setSyncInPulseSource(myEPWM2_BASE, EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM1);
    EPWM_enablePhaseShiftLoad(myEPWM2_BASE);

    // Calculate delays
    get_delays_FED_RED(myEPWM1_BASE, tbclk);
    get_delays_FED_RED(myEPWM2_BASE, tbclk);

    // Enable sync and clock to PWM
    SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_TBCLKSYNC);

    // Enable Global Interrupt (INTM) and realtime interrupt (DBGM)
    EINT;
    ERTM;

    while(1)
    {
        // Trip flag is set when CTRIP signal is asserted
        if((EPWM_getTripZoneFlagStatus(myEPWM1_BASE) & EPWM_TZ_FLAG_OST) != 0U && (EPWM_getTripZoneFlagStatus(myEPWM2_BASE) & EPWM_TZ_FLAG_OST) != 0U)
        {
            // Wait for comparator CTRIP to de-assert
            while((CMPSS_getStatus(CMPSS1_BASE) & CMPSS_STS_HI_FILTOUT) != 0U && (CMPSS_getStatus(CMPSS2_BASE) & CMPSS_STS_HI_FILTOUT) != 0U)
            {
            }
            // Clear trip flags
            EPWM_clearTripZoneFlag(myEPWM1_BASE, EPWM_TZ_INTERRUPT | EPWM_TZ_FLAG_OST);
            EPWM_clearTripZoneFlag(myEPWM2_BASE, EPWM_TZ_INTERRUPT | EPWM_TZ_FLAG_OST);
        }
    }
}

float init_EPWM(base)
{
    float PWM_TBPRD;
    float PWM_CMPA;
    EPWM_ClockDivider PWM_PARAM_PRESCALER;
    EPWM_HSClockDivider PWM_PARAM_HIGHSPEEDPRESCALER;
    float TBCLK;

    get_pwm_clock_from_freq(&PWM_TBPRD , &PWM_CMPA , &PWM_PARAM_PRESCALER , &PWM_PARAM_HIGHSPEEDPRESCALER, &TBCLK);

    // Parameters
    EPWM_setTimeBasePeriod(base, (uint16_t)PWM_TBPRD);
    EPWM_setCounterCompareValue(base, EPWM_COUNTER_COMPARE_A, (uint16_t)PWM_CMPA);
    EPWM_setPhaseShift(base, 0U);
    EPWM_setTimeBaseCounter(base, 0U);
    EPWM_setTimeBaseCounterMode(base, EPWM_COUNTER_MODE_UP_DOWN);
    EPWM_disablePhaseShiftLoad(base);
    EPWM_setClockPrescaler(base, PWM_PARAM_PRESCALER, PWM_PARAM_HIGHSPEEDPRESCALER);

    // Set up shadowing
    EPWM_setCounterCompareShadowLoadMode(base, EPWM_COUNTER_COMPARE_A, EPWM_COMP_LOAD_ON_CNTR_ZERO);

    // Set actions
    EPWM_setActionQualifierAction(base, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_HIGH, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA);
    EPWM_setActionQualifierAction(base, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_LOW, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPA);
    EPWM_setActionQualifierAction(base, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_HIGH, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA);
    EPWM_setActionQualifierAction(base, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_LOW, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPA);

    // Trip zone
    // Configure ePWM1x to output low on TZx TRIP
    EPWM_setTripZoneAction(base, EPWM_TZ_ACTION_EVENT_TZA, EPWM_TZ_ACTION_LOW);
    EPWM_setTripZoneAction(base, EPWM_TZ_ACTION_EVENT_TZB, EPWM_TZ_ACTION_LOW);
    // Trigger event when DCBH is high
    EPWM_setTripZoneDigitalCompareEventCondition(base, EPWM_TZ_DC_OUTPUT_B1, EPWM_TZ_EVENT_DCXH_HIGH);
    // Configure DCBH to use TRIP4 as an input
    EPWM_enableDigitalCompareTripCombinationInput(base, EPWM_DC_COMBINATIONAL_TRIPIN4, EPWM_DC_TYPE_DCBH);
    // Enable DCB as OST
    EPWM_enableTripZoneSignals(base, EPWM_TZ_SIGNAL_DCBEVT1);
    // Configure the DCB path to be unfiltered and asynchronous
    EPWM_setDigitalCompareEventSource(base, EPWM_DC_MODULE_B, EPWM_DC_EVENT_1, EPWM_DC_EVENT_SOURCE_ORIG_SIGNAL);

    // To use CMPx_LP
    //AIO224 -> myAIO0 Pinmux
    GPIO_setPinConfig(GPIO_226_GPIO226);
    //AIO237 -> myAIO0 Pinmux
    GPIO_setPinConfig(GPIO_237_GPIO237);
    //AIO226 -> myAIO2 Pinmux
    GPIO_setPinConfig(GPIO_230_GPIO230);
    // To use CMP1_HP0
    ASysCtl_selectCMPLPMux(ASYSCTL_CMPLPMUX_SELECT_1, 1);
    // To use CMP2_HN1
    ASysCtl_selectCMPLPMux(ASYSCTL_CMPLPMUX_SELECT_2, 3);
    // To use CMP3_HP0
    ASysCtl_selectCMPLPMux(ASYSCTL_CMPLPMUX_SELECT_3, 0);

    XBAR_setEPWMMuxConfig(XBAR_TRIP4, XBAR_EPWM_MUX01_CMPSS1_CTRIPL);
    XBAR_setEPWMMuxConfig(XBAR_TRIP4, XBAR_EPWM_MUX03_CMPSS2_CTRIPL);
    XBAR_setEPWMMuxConfig(XBAR_TRIP4, XBAR_EPWM_MUX05_CMPSS3_CTRIPL);

    XBAR_enableEPWMMux(XBAR_TRIP4, XBAR_MUX01 | XBAR_MUX03 | XBAR_MUX05);

    // Clear trip flags
    EPWM_clearTripZoneFlag(base, EPWM_TZ_INTERRUPT | EPWM_TZ_FLAG_OST);
    return TBCLK;
}

void set_delays(uint32_t base, uint16_t DBFED, uint16_t DBRED)
{
    // Sets up the rising edge delay input signal.
    EPWM_setFallingEdgeDeadBandDelayInput(base, EPWM_DB_INPUT_EPWMA);
    // Sets up the falling edge delay input signal.
    EPWM_setRisingEdgeDeadBandDelayInput(base, EPWM_DB_INPUT_EPWMA);
    // This function sets the FED count value, this one should be less than 16384.
    EPWM_setFallingEdgeDelayCount(base, DBFED);
    // This function sets the RED count value, this one should be less than 16384.
    EPWM_setRisingEdgeDelayCount(base, DBRED);
    // This function sets up the polarity : EPWM_DB_POLARITY_ACTIVE_HIGH => polarity is not inverted and EPWM_DB_POLARITY_ACTIVE_LOW => polarity is inverted.
    EPWM_setDeadBandDelayPolarity(base, EPWM_DB_RED, EPWM_DB_POLARITY_ACTIVE_HIGH);
    EPWM_setDeadBandDelayPolarity(base, EPWM_DB_FED, EPWM_DB_POLARITY_ACTIVE_HIGH);
    // This function sets up the dead band delay mode. The enableDelayMode determines if a dead band delay should be applied.
    EPWM_setDeadBandDelayMode(base, EPWM_DB_RED, true);
    EPWM_setDeadBandDelayMode(base, EPWM_DB_FED, true);
    //EPWM_setDeadBandOutputSwapMode(myEPWM2_BASE, EPWM_DB_OUTPUT_A, false);
    EPWM_setDeadBandOutputSwapMode(base, EPWM_DB_OUTPUT_B, false);
}

void init_cmpss(base)
{
    // Enable CMPSS and configure the negative input signal to come from the DAC
    CMPSS_enableModule(base);
    CMPSS_configHighComparator(base, CMPSS_INSRC_DAC);
    CMPSS_configLowComparator(base, CMPSS_INSRC_DAC);
    // Use VDDA as the reference for the DAC and set DAC value to midpoint for arbitrary reference.
    CMPSS_configDAC(base, CMPSS_DACREF_VDDA | CMPSS_DACVAL_SYSCLK | CMPSS_DACSRC_SHDW);
    CMPSS_setDACValueHigh(base, 1024);
    // Configure the output signals. Both CTRIPH will be fed by the synchronous comparator output.
    CMPSS_configOutputsHigh(base, CMPSS_TRIP_SYNC_COMP);
    CMPSS_configOutputsLow(base, CMPSS_TRIP_SYNC_COMP);
}

What's the effect about this function : CMPSS_configOutputsLow(base, CMPSS_TRIP_SYNC_COMP) ?

Can you help me please ?

Thanks

Damien

Hi Damien,

Looking at your configuration code for differences between COMPH and COMPL, I see that you are not configuring DACVAL for COMPL.

    CMPSS_setDACValueHigh(base, 1024);

Try setting DACValueLow also to 1024 and see if that works. I'll be OOO tomorrow so if the suggestion above doesn't work, I'll look at your reply early next week.

Hi Frank

I found my mistake after writing at the forum so sorry, yes it's this. I will think of benefits next time. Sorry again !

Thanks

Damien

No problem. Let us know if you ran into anymore issues.