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TMS320F28388D: Doesn't CM Memory(ex. C1 RAM, CM to CPU1 MSGRAM0 ...) use cache memory?

Meili
Prodigy 40 points

Part Number: TMS320F28388D
Other Parts Discussed in Thread: TMS320C6678

Hello, I had a problem using TMS320F28388D.

Does cache not exist in TMS320F28388D?

I'm going to write random values to CM memory (ex. C1 RAM, CM to CPU1 MSGRAM0 ...).

The previously used chips had cache, so they wrote data through the cache_inv, cache_wb process, but the TMS320F28388D manual did not find any related information.

Is there any code in CM memory (ex. C1 RAM, CM to CPU1 MSGRAM0...) that I need to perform when I write data?

If there is a process to write data in CM memory, I would appreciate it if you could let me know the relevant contents or example location.

Thank you!

  • 0
    TI__Guru** 117371 points

    Hi,

    Meili said:
    The previously used chips had cache, so they wrote data through the cache_inv, cache_wb process

    Which device you are referring here ? 

    Meili said:
    Is there any code in CM memory (ex. C1 RAM, CM to CPU1 MSGRAM0...) that I need to perform when I write data?

    I am not clear on this query. You need to write/read data like normal read/write operation. There is no special process needed for that.

    Regards,

    Vivek Singh

  • 0 in reply to Vivek Singh
    Prodigy 40 points
    Vivek Singh said:
    Which device you are referring here ? 

    The chip I referred to is TMS320C6678. When using TMS320C6678, I used cache memory when writing data to DPRAM.

    Vivek Singh said:
    I am not clear on this query. You need to write/read data like normal read/write operation. There is no special process needed for that.

    I thought there was a minimum access unit in memory like when using cache memory.

    But I just have to write in the normal way, right? Thank you!

  • +1 in reply to Meili
    TI__Guru** 117371 points
    Meili said:
    The chip I referred to is TMS320C6678. When using TMS320C6678, I used cache memory when writing data to DPRAM

    OK, thanks. That device is from different business group of TI hence has different architecture. 

    Meili said:

    I thought there was a minimum access unit in memory like when using cache memory.

    But I just have to write in the normal way, right? Thank you!

    Correct. It's normal memory hence need to be written in the normal way. 

    Regards,

    Vivek Singh