TMS320F280025: Nesting Interrupts with Priority levels

Ahmed Abdalla

Hi,

According to the information provided in this link: https://software-dl.ti.com/C2000/docs/c28x_interrupt_nesting/html/index.html

I cannot enable interrupts outside the ISR group by setting the PIEIER register in the ISR. For example, if I'm in ADCA1 ISR I cannot enable EPWM1 PIEIER bit to have higher priority than ADCA1 since it is in group 3.

In the document, it says I have to follow "Disabling Interrupts" section in the TRM. Can you please provide more information on this point? Is it that I have to disable all interrupts first before

enabling the other group interrupts? What if I just set the PIEIER bit of the desired interrupt just after I set the IER bit? What will happen?

Thanks,

Ahmed

over 4 years ago

0 Veena Kamath over 4 years ago

TI__Mastermind 32695 points

Hi Ahmed,

Your query has been forwarded to an expert, you will get a response soon.

Regards,

Veena

0 Vasudha Bhadoria over 4 years ago

TI__Genius 10845 points

Hi Ahmed,

Ahmed Abdalla said:
In the document, it says I have to follow "Disabling Interrupts" section in the TRM. Can you please provide more information on this point? Is it that I have to disable all interrupts first before

PFB the details as per TRM on disabling interrupts. This is primarily done to avoid any spurious interrupts.

Individual interrupts can be disabled using the PIEIERx registers, but care must be taken to avoid race
conditions. If an interrupt signal is already propagating when the PIEIER write completes, it may reach the
CPU and trigger a spurious interrupt condition. To avoid this, use the following procedure:
1. Disable interrupts globally (DINT or SETC INTM).
2. Clear the PIEIER bit for the interrupt.
3. Wait 5 cycles to make sure that any propagating interrupt has reached the CPU IFR register.
4. Clear the CPU IFR bit for the interrupt's PIE group.
5. Clear the PIEACK bit for the interrupt's PIE group.
6. Enable interrupts globally (EINT or CLRC INTM).
Interrupt groups can be disabled using the CPU IER register. This cannot cause a race condition, so no
special procedure is needed.

Thanks
Vasudha

0 Ahmed Abdalla over 4 years ago in reply to Vasudha Bhadoria

Prodigy 130 points

Hi Vashuda,

Thanks for your response. I understand the procedure in the TRM. My concern is why should I disable the interrupts. For example, I'm in ADCA1 ISR which has highest priority in PIE table, but in my application, EPWM1 interrupt has higher priority but it is in group 3 of the PIE table. So, to prioritize EPMW1 over ADCA1, the way I would nest the interrupts in the ADCA1 ISR is as follows:

IER |= M_INT3;
IER &= M_INT3;

// Enable PIE interrupt group 3
PieCtrlRegs.PIEIER3.bit.INTx1 = 1;

// Clear ACK to allow group 3 INT
PieCtrlRegs.PIEACK.bit.ACK3 = 1;

According to my understanding of the information in the TI link, this shouldn't be done in ADCA1 and I should follow "Disabling Interrupts" in the TRM. My question is: what is wrong with the above approach? If it can cause spurious interrupts, what is the correct procedure to prioritize EPWM1 interrupt over ADCA1?

Thanks

0 Vasudha Bhadoria over 4 years ago in reply to Ahmed Abdalla

TI__Genius 10845 points

Hi Ahmed,

I think the code snippet shown in the above reply might work for just these 2 interuupts but the logic explained in the interrupt nesting link shows a generic approach for performing the software prioritization of interrupt and is scalable for any number of interrupts in the system.

E.g. If more interrupts from group 3 were to be added in your application, how would you define priority among the same group interrupts with the approach shown above. With the above approach, the default hardware priority would be used for the interrupts enabled with in the same group.

#if (G1_1PL != 0)
__interrupt void ADCA1_ISR(void)     // ADC
{
    // Set interrupt priority:
    volatile uint16_t TempPIEIER = PieCtrlRegs.PIEIER1.all;
    IER |= M_INT1;
    IER    &= MINT1;                         // Set "global" priority
    PieCtrlRegs.PIEIER1.all &= MG1_1;   // Set "group"  priority
    PieCtrlRegs.PIEACK.all = 0xFFFF;   // Enable PIE interrupts
    __asm("  NOP");
    EINT;

    //
    // Insert ISR Code here
    //
    for(i = 1; i <= 10; i++) {}

    //
    // Restore registers saved:
    //
    DINT;
    PieCtrlRegs.PIEIER1.all = TempPIEIER;

    //
    //  Add ISR to Trace
    //
    ISRTrace[ISRTraceIndex] = 0x0011;
    ISRTraceIndex++;

}
#endif

In the interrupt nesting approach shown in the TI link, the general idea is to configure the global priority in such a way that only groups with higher priority than the current interrupt group is enabled using the macro MINT1. The same group is enabled using the macro M_INT1 and then the same group higher priority interrupts are enabled through the macro MG1_1 (enables all the same group interrupts which have higher priority than 1.1 interrupt).

Let me know if this resolves your query.

Thanks
Vasudha

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TMS320F280025: Nesting Interrupts with Priority levels