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Piccolo SPI Port Issues

John Wilkes
Expert 1315 points

Hi,

I have noticed a couple of things that I don't understand on the Piccolo SPI port and together, they are causing me grief:

1. The port is set up as a slave and receives data which is duely read out of the FIFO. At some point later the SPI is turned into a master by setting the SPICTL MASTER_SLAVE bit. Immediately this bit is set the port transmits the data it received earlier - at no point was data loaded into TX buffer and the transmiision is unasked for and unwanted. The only way I have found of getting round this is to hold the port in reset using the SPICCR SPISWRESET pin while the MASTER_SLAVE pin is set. This stops the rogue transmission but leads to the second problem:

2. When in reset and MASTER_SLAVE bit is set, the SPICLK line is driven low. SPRUG71b says that the clock should go to its inactive level (page 25). I have CLOCK_POLARITY set to 1, so the inactive level should surey be high?

Can anyone help me get round, or even just explain, these two things?

Cheers,

John.

  • 0
    TI__Expert 3760 points

    John:

    1. Regarding your first question,  the reason for this is that the SPI transmit and receive buffer share the same SPIDAT register, so the data that you received remains in the SPIDAT register when you switch from slave to master (therefore your original slave input becomes a master output, and the data gets transmitted). 
      1. As mentioned in the documentation, when changing ANY SPI configuration, the SPI SW RESET bit should be cleared -> change initialization/configuration bits -> Set SPI SW RESET bit. It seems you are already doing this to handle this condition
    2. The SPICLK signal output returns to its inactive level ONLY if the module is operating as master when SPI SW RESET bit is cleared. Yes, when CLOCK POLARITY = 1, the clock would be high when inactive.
  • 0 in reply to Chrissy Chang
    Expert 1315 points

    Hi Chrissy,

    Thanks for your response. I think this all makes sense now. Just to clarify the second point though. Prior to the sequence, the SPI port is enabled as a slave with the clock polarity bit set. The SPICLK input is high (actually it is un-driven at this point but pulled high). Then:

    1. SpiaRegs.SPICCR.bit.SPISWRESET = 0;

    SPICLK pin stays high

     

    2. SpiaRegs.SPICTL.bit.MASTER_SLAVE = 1;

     

    SPICLK pin goes low

     

    3. SpiaRegs.SPICCR.bit.SPISWRESET = 1;

     

    SPICLK goes high.

    Is this the operation expected?

    Cheers,

    John.

     

  • 0 in reply to John Wilkes
    TI__Expert 3760 points

    John -

    I tested this in silicon and have verified the same results that you are seeing.

    That statement in the user guide is incorrect and should actually be the condition when in master mode and SPI SW RESET is released (=1) prior to data being transmitted.

  • 0 in reply to Chrissy Chang
    Expert 1315 points

    Chrissy,

    Thanks for your reply. Thank you for confirming the expected operation. Unfortunately, the clock line going low during this transistion from master to slave causes me a bit of a headache because the slave waiting for data see this as a clock edge and resulting data is one bit shifted (and one bit lost). I have got around this by externally gating the clock with another GPIO line which I can use to mask the clock line while the transistion takes place. It's a bit of extra stuff to do, but it works.

    Thanks again for your help.

    Cheers,

    John.