TMS320F280025: 3 wire SPI

Apologies for the delayed response. Unfortunately, we do not have an example in C2000ware which configures the SPI in 3 wire mode.

Can you please confirm that the TRIWIRE register bit is set in both the devices?

Have you already checked the section "SPI 3-Wire Mode Code Examples" in the device TRM?

Regards,

Veena

Yes, TRIWIRE is activated in both devices.

The issue was later found to be the STE signal from the master. The duration was insufficient for the length of the packet, although the clock & actual SIMO signals were good.

We checked both by initializing the pin as the SPI peripheral (SPIB_STE) & as a GPIO (with manual set and reset before and after the transmit function). In both cases, the signal duration was less than what is required.

By configuring the STE pin as a GPIO & setting it to enable permanently, we were able to receive the packet on the slave. Although this is probably not a good solution.

I think there is an issue with TMS320F280049C's SPI_STE pin as this problem was observed in another project where we tried to communicate with 49C(master) and MSP430G2744(slave).

BTW, in the other project we were using the SPI in 4 wire configuration.

Hi Srikrishna,

The timing parameters are specified in the device datasheet. Are you seeing it differently while observing in an oscilloscope?

Regards,

Veena

Hi Veena,

Yes, I'm observing different timing in the scope. I'm transmitting eight 16-bit values (I'm using SPI in 16bit format), which uses128 clock cycles.

When using the pin as GPIO, the STE goes to LOW for only about a tenth of the duration.

Another issue I faced was, when the pin was enabled as a peripheral (SPI_STE), the SIMO signal had a logic high level of only 1.7V (must be 3.3). Hence, this data was not detected by even the master during a readback.

Thanks

Srikrishna

Hi Srikrishna,

I will loop in the SPI design experts

Regards,

Veena

SriKrishna,

Can you share your master / slave code? Also, are you using FIFO / non-FIFO mode?

Any oscilloscope snapshots you can share.

Regards,

Manoj

Hello Manoj,

Right now, I haven't enabled FIFO. I don't think we're planning to use it.

Master Init:-

Master Transmit:-

In transmit, the STE pin in currently used as a GPIO which is enabled (set to LOW) permanently. 8 16-bit values are transmitted from 0x0000, 0x1111,...,0x7777.

Slave Init:-

Slave Receive:-

When the STE pin was enabled as a peripheral, the master out signal had a voltage level of 0 to about 1.7 which is insufficient. The below image of the oscilloscope shows CLK (in green from 0 to 3.3V) & SIMO (in yellow from 0 to 1.7V).

When the pin is used as a GPIO and toggled manually, we're observing the required behavior on the SIMO.

I do not have an image of the STE signal, but when toggled manually (before & after the master transmit function), it had a duration of about 1/8 the clock duration.

Thanks

Srikrishna

Srikrishna,

You have enabled fifo in master init code. Did you try disabling that?

Regards,

Manoj