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Original question:

How do I calculate the ADC sample rate for C2000 Type 3 (e.g. F28069) and Type 4 (e.g. F280049) ADCs?

TMS320F280049: ADC conversion time calculation

Lei Ding
Prodigy 80 points
Part Number: TMS320F280049


The ADC conversion time (including S&H and conversion) in the data sheet (Table 5-1, 290ns, 3.45MSPS).

The datasheet also says that the ADC conversion cycles is 11 ADCCLK cycles with ADCCLK = 100 MHz sysclk. Does this mean that ADC conversion time is 110ns? The S&H time is 170ns?

  • 0
    TI__Mastermind 38830 points

    Hi Lei,

    Some clarifications:

            - Minimum SH for F280049 in DS is 75ns but that will not be realized for a 100MHz clk (10nS period) so the min SH will be rounded to 80ns or 8 SYSCLK cycles (Table 7.10.1.2.1)

            - For a 100MHz SYSCLK and to meet a 50MHz ADC clk, ADC prescale has to be set to div by 2.  Referring to table 7-17 ADC Timings, this setting corresponds to 10.5 ADCLK cycles or 21 SYSCLK cycles.

            - Overall conversion time is min SH + ADC quantization time or 8 SYSCLK cycles + 21 SYSCLK cycle or 29 SYSCLK cycles overall.  29 x 10ns = 290 SYSCLK cycles for one conversion, or 3.45MSPS.

    Regards,

    Joseph