LAUNCHXL-F280049C: ADCB1 interrupt coming but ADC results are not updated in result register. ADC values stuck to single value of 127

Deepak Kadam

Part Number: LAUNCHXL-F280049C
Other Parts Discussed in Thread: C2000WARE

Hi,

I am configuring ADC with SOC from Timer0 running at 55us period. I am getting ADC interrupts but ADCA, ADCB or ADCC values not getting updated.

I have also observed once

Fullscreen cpu_timers_isr.c Download

//###########################################################################
//
// FILE:   cpu_timers_isr.c
//
// TITLE:  CPU Timers ISRs for F2837xD.
//
//
//###########################################################################
//
// Included Files
//
#include <sfc/sfc_comp.h>
#include <sfc/sfc_params.h>
#include "F28x_Project.h"
#include "tick.h"
#include "epwm.h"
#include "clarke.h"
#include "park.h"
#include "hw.h"
#include "spll.h"
#include "spll_regulator.h"

#if(SFC_SYNCHORINSE_WITH_INPUT_3PHASE == (1))
 static float xn1 = 0,xA1=0;
 static float yn1 = 1;

 static float xn2 = 0.8666,xA2=0;
 static float yn2 = -0.5064;

 static float xn3 = -0.8648,xA3=0;
 static float yn3 = -0.4946;

#endif
 void Task_100usDummy(void);
 float32 VDCLinlkPrev = 0.0, IDCLinlkPrev = 0.0;


#if(ADC_READINGS_AVERAGING_ENABLED == true)

#define MOVING_AVERAGE_FILTER_SIZE  (5)

 static int32 Adc_VInA[MOVING_AVERAGE_FILTER_SIZE],Adc_VInB[MOVING_AVERAGE_FILTER_SIZE],Adc_VInC[MOVING_AVERAGE_FILTER_SIZE],Adc_VDCOut[MOVING_AVERAGE_FILTER_SIZE];
 static int32 Adc_CInA[MOVING_AVERAGE_FILTER_SIZE],Adc_CInB[MOVING_AVERAGE_FILTER_SIZE],Adc_CInC[MOVING_AVERAGE_FILTER_SIZE],Adc_CDCOut[MOVING_AVERAGE_FILTER_SIZE];

//
// Function Prototypes for interrupts
//
__interrupt void cpu_timer0_isr(void);
__interrupt void cpu_timer1_isr(void);
__interrupt void cpu_timer2_isr(void);

Uint16 i =0;

//
// cpu_timer0_isr - CPU Timer0 ISR with interrupt counter
//
__interrupt void cpu_timer0_isr(void)
{
    /* increment 55 us counter */
    CpuTimer0.InterruptCount++;

    if( CpuTimer0.InterruptCount >= 6000) // LED blink rate 55us*6000= 330ms
    {
        CpuTimer0.InterruptCount = 0;
        /* Toggle Heart-bit LED */
        GpioDataRegs.GPBTOGGLE.bit.GPIO40 = 1;
    }
    else
    {
        //CpuTimer0.InterruptCount = 1;
    }

    Task_100usDummy();

    /* Calculate RMS voltage from Input reading ADC count */
    HW_ComputeAcRmsVoltageInputs();

    /* Run SPLL to compute Theta, d and Q for voltage and currents */
    Spll_Loop();

    /* Run voltage regulator PID loop */
    SpllReg_Loop();



   //
   // Acknowledge this interrupt to receive more interrupts from group 1
   //
   PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;
}

//
// cpu_timer1_isr - CPU Timer1 ISR --100us tick timer for state machine operations
//
__interrupt void cpu_timer1_isr(void)
{
   if( CpuTimer1.InterruptCount == 1)
   {
       CpuTimer1.InterruptCount = 0;
   }
   else
   {
       CpuTimer1.InterruptCount = 1;
   }
   //Tick_100us_Tasks();
}

Uint16 CPU2_Timer_Count = 0;
//
// cpu_timer2_isr CPU Timer2 ISR ( 1ous tick timer used for ADC conversion*/
//
__interrupt void cpu_timer2_isr(void)
{
    CPU2_Timer_Count++;

    if(CPU2_Timer_Count >= 10)
    {
        //Tick_100us_Tasks();
        //CPU2_Timer_Count = 0;
    }


    /* Capture Input Voltage ADC readings every 10us */
     Adc_VInA[CpuTimer2.InterruptCount] = (int32)AdcaResultRegs.ADCRESULT0;
     Adc_VInB[CpuTimer2.InterruptCount] = (int32)AdcaResultRegs.ADCRESULT1;
     Adc_VInC[CpuTimer2.InterruptCount] = (int32)AdcaResultRegs.ADCRESULT2;

     /* Capture Output DC Link Voltage ADC reading every 10us */
     Adc_VDCOut[CpuTimer2.InterruptCount] = (int32)AdcbResultRegs.ADCRESULT0;

     /* Capture Input Current ADC readings every 10us */
     Adc_CInA[CpuTimer2.InterruptCount] = (int32)AdcaResultRegs.ADCRESULT3;
     Adc_CInB[CpuTimer2.InterruptCount] = (int32)AdcaResultRegs.ADCRESULT4;
     Adc_CInC[CpuTimer2.InterruptCount] = (int32)AdcaResultRegs.ADCRESULT5;

     /* Capture Output DC Link Current ADC reading every 10us */
     Adc_CDCOut[CpuTimer2.InterruptCount] = (int32)AdcbResultRegs.ADCRESULT1;

     CpuTimer2.InterruptCount++;

}


void Task_100usDummy(void)
{
    //Tick_100us_Tasks();
}
//
// End of file
//

that in IFR register , INT1 bit is always set and not getting cleared.'

I want to sample channels ADCA0 to A9 , B0,B1,B4 and C0,C2, C4 using single SOC (Timer0 or Timer2).

I have attached ADC and main configuration for reference.

Fullscreen ext_interrupt.c Download

/*
 * ext_interrupt.c
 *
 *  Created on: 19-Nov-2020
 *      Author: Shree
 */

#include <sfc/sfc_comp.h>
#include "F28x_Project.h"
#include "ext_interrupt.h"
#include "epwm.h"

extern SFC_ERROR_TYPE SfcErrorCode;

interrupt void xint1_isr(void);
interrupt void xint2_isr(void);
interrupt void xint3_isr(void);
volatile Uint32 Xint1Count;
volatile Uint32 Xint2Count;
volatile Uint32 Xint3Count;


void ExtInterrupt_Init(void)
{
    //
    // Clear the counters
    //
    Xint1Count = 0; // Count XINT1 interrupts
    Xint2Count = 0; // Count XINT2 interrupts
    Xint3Count = 0; // Count XINT2 interrupts

    //
    // GPIO0 and GPIO1 are inputs
    //
    EALLOW;
    GpioCtrlRegs.GPBMUX2.bit.GPIO49 = 0;         // GPIO
    GpioCtrlRegs.GPBDIR.bit.GPIO49 = 0;          // input
    GpioCtrlRegs.GPBQSEL2.bit.GPIO49 = 0;        // XINT1 Synch to SYSCLKOUT only

    GpioCtrlRegs.GPBMUX2.bit.GPIO50 = 0;         // GPIO
    GpioCtrlRegs.GPBDIR.bit.GPIO50 = 0;          // input
    GpioCtrlRegs.GPBQSEL2.bit.GPIO50 = 2;        // XINT2 Qual using 6 samples
    GpioCtrlRegs.GPBCTRL.bit.QUALPRD2 = 0xFF;   // Each sampling window is 510*SYSCLKOUT for input 48 to 55

    GpioCtrlRegs.GPBMUX2.bit.GPIO51 = 0;         // GPIO
    GpioCtrlRegs.GPBDIR.bit.GPIO51 = 0;          // input
    GpioCtrlRegs.GPBQSEL2.bit.GPIO51 = 0;        // XINT1 Synch to SYSCLKOUT only
    EDIS;

    //
    // GPIO0 is XINT1, GPIO1 is XINT2
    //
   GPIO_SetupXINT1Gpio(49);
   GPIO_SetupXINT2Gpio(50);
   GPIO_SetupXINT3Gpio(51);

   //
   // Configure XINT1
   //
      XintRegs.XINT1CR.bit.POLARITY = 1;          // Falling edge interrupt
      XintRegs.XINT2CR.bit.POLARITY = 1;          // Rising edge interrupt
      XintRegs.XINT3CR.bit.POLARITY = 1;          // Rising edge interrupt

   //
   // Enable XINT1 and XINT2
   //
      XintRegs.XINT1CR.bit.ENABLE = 1;            // Enable XINT1
      XintRegs.XINT2CR.bit.ENABLE = 1;            // Enable XINT2
      XintRegs.XINT3CR.bit.ENABLE = 1;            // Enable XINT3

}


//
// xint1_isr - External Interrupt 1 ISR
//
interrupt void xint1_isr(void)
{
    Xint1Count++;

    /* Toggle Heart-bit LED */
    GpioDataRegs.GPBTOGGLE.bit.GPIO33 = 1;

    Epwm_ShufOffSfcPWM();
    SfcErrorCode = ERROR_EXTERNAL_IGBT_FAULT;

    //
    // Acknowledge this interrupt to get more from group 1
    //
    PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;
}

//
// xint2_isr - External Interrupt 2 ISR
//
interrupt void xint2_isr(void)
{
    Xint2Count++;

    /* Toggle Heart-bit LED */
        GpioDataRegs.GPBTOGGLE.bit.GPIO33 = 1;

        Epwm_ShufOffSfcPWM();
        SfcErrorCode = ERROR_EXTERNAL_OVERTEMP_FAULT;

    //
    // Acknowledge this interrupt to get more from group 1
    //
    PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;
}

//
// xint2_isr - External Interrupt 2 ISR
//
interrupt void xint3_isr(void)
{
    Xint3Count++;

    /* Toggle Heart-bit LED */
    GpioDataRegs.GPBTOGGLE.bit.GPIO33 = 1;

    Epwm_ShufOffSfcPWM();
    SfcErrorCode = ERROR_EXTERNAL_ECU_FAULT;

    //
    // Acknowledge this interrupt to get more from group 1
    //
    PieCtrlRegs.PIEACK.all = PIEACK_GROUP12;
}

Fullscreen 3704.main.c Download

//###########################################################################
//
// FILE:   cpu_Timers_cpu01.c
//
// TITLE:  Cpu Timers Example for F2837xD.
//
//! \addtogroup cpu01_example_list
//! <h1> CPU Timers </h1>
//!
//! This example configures CPU Timer0, 1, and 2 and increments
//! a counter each time the timer asserts an interrupt.
//!
//! \b Watch \b Variables \n
//! - CpuTimer0.InterruptCount
//! - CpuTimer1.InterruptCount
//! - CpuTimer2.InterruptCount
//!
//
//###########################################################################
// $TI Release: F2837xD Support Library v3.06.00.00 $
// $Release Date: Mon May 27 06:48:24 CDT 2019 $
// $Copyright:
// Copyright (C) 2013-2019 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without 
// modification, are permitted provided that the following conditions 
// are met:
// 
//   Redistributions of source code must retain the above copyright 
//   notice, this list of conditions and the following disclaimer.
// 
//   Redistributions in binary form must reproduce the above copyright
//   notice, this list of conditions and the following disclaimer in the 
//   documentation and/or other materials provided with the   
//   distribution.
// 
//   Neither the name of Texas Instruments Incorporated nor the names of
//   its contributors may be used to endorse or promote products derived
//   from this software without specific prior written permission.
// 
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################

//
// Included Files
//
#include <sfc/sfc_comp.h>
#include <sfc/sfc_params.h>
#include <sfc/sfc_smd.h>
#include "F28x_Project.h"
#include "adc.h"
#include "epwm.h"
#include "spll.h"
#include "spll_regulator.h"
#include "sci_uart.h"
#include "modbus.h"
#include "ext_interrupt.h"
//
// Function Prototypes
//

extern __interrupt void cpu_timer0_isr(void);
extern __interrupt void cpu_timer1_isr(void);
extern __interrupt void cpu_timer2_isr(void);
extern __interrupt void adcA1ISR(void);
extern __interrupt void adcB1ISR(void);
extern __interrupt void adcC1ISR(void);
void main(void)
{
    char *msg;
    Uint32 i=0;
    //
    // Step 1. Initialize System Control:
    // PLL, WatchDog, enable Peripheral Clocks
    // This example function is found in the F2837xD_SysCtrl.c file.
    //
    InitSysCtrl();

    //
    // Step 2. Initialize GPIO:
    // This example function is found in the F2837xD_Gpio.c file and
    // illustrates how to set the GPIO to it's default state.
    //
    InitGpio();
    InitEPwm1Gpio();    // Configure EPWM1 GPIO pins
    InitEPwm2Gpio();    // Configure EPWM1 GPIO pins
    InitEPwm3Gpio();    // Configure EPWM2 GPIO pins
    InitEPwm4Gpio();    // Configure EPWM1 GPIO pins
    InitEPwm5Gpio();    // Configure EPWM1 GPIO pins

    InitEPwm6Gpio();    // Configure EPWM2 GPIO pins
    InitEPwm7Gpio();    // Configure EPWM2 GPIO pins
    InitEPwm8Gpio();    // Configure EPWM2 GPIO pins

    GPIO_SetupPinMux(65, GPIO_MUX_CPU1, 0);
    GPIO_SetupPinOptions(65, GPIO_OUTPUT, GPIO_PUSHPULL);

    GPIO_SetupPinMux(71, GPIO_MUX_CPU1, 0);
    GPIO_SetupPinOptions(71, GPIO_OUTPUT, GPIO_PUSHPULL);

    //
    // Step 3. Clear all interrupts and initialize PIE vector table:
    // Disable CPU interrupts
    //
    DINT;

    //
    // Initialize the PIE control registers to their default state.
    // The default state is all PIE interrupts disabled and flags
    // are cleared.
    // This function is found in the F2837xD_PieCtrl.c file.
    //
    InitPieCtrl();

    //
    // Disable CPU interrupts and clear all CPU interrupt flags:
    //
    IER = 0x0000;
    IFR = 0x0000;

    //
    // Initialize the PIE vector table with pointers to the shell Interrupt
    // Service Routines (ISR).
    // This will populate the entire table, even if the interrupt
    // is not used in this example.  This is useful for debug purposes.
    // The shell ISR routines are found in F2837xD_DefaultIsr.c.
    // This function is found in F2837xD_PieVect.c.
    //
    InitPieVectTable();

    //
    // Configure the ADC and power it up
    //
    ADC_ConfigureADC();

    Epwm_InitEPwm1();
    Epwm_InitEPwm2();
    Epwm_InitEPwm3();
    Epwm_InitEPwm4();
    Epwm_InitEPwm5();
    Epwm_InitEPwm6();
    Epwm_InitEPwm7();
    Epwm_InitEPwm8();

    //
    // Setup the ADC for continuous conversions
    //
    ADC_SetupADCContinuous();
    //
    // Step 4. Initialize the Device Peripheral. This function can be
    //         found in F2837xD_CpuTimers.c
    //
    InitCpuTimers();   // For this example, only initialize the Cpu Timers

    //
    // Configure CPU-Timer 0, 1, and 2 to interrupt every second:
    // 200MHz CPU Freq, 1 second Period (in uSeconds)
    //
    /* CPU Timer for 55.55us sampling (i.e.at 1degree electrical) of incoming 3phase sine wave.*/
    ConfigCpuTimer(&CpuTimer0, CPU_FREQ_MHZ, CPU_TIMER0_PERIOD_US);
    //ConfigCpuTimer(&CpuTimer1, CPU_FREQ_MHZ, CPU_TIMER1_PERIOD_US);
    /* Configure CPU2 Timer for 25us. This timer will be used as SOC trigger for ADC so kept sampling @10us */
    ConfigCpuTimer(&CpuTimer2, CPU_FREQ_MHZ, CPU_TIMER2_PERIOD_US);

    //
    // To ensure precise timing, use write-only instructions to write to the
    // entire register. Therefore, if any of the configuration bits are changed in
    // ConfigCpuTimer and InitCpuTimers (in F2837xD_cputimervars.h), the below
    // settings must also be updated.
    //
    CpuTimer0Regs.TCR.all = 0x4000;
    CpuTimer1Regs.TCR.all = 0x4000;
    CpuTimer2Regs.TCR.all = 0x4000;

    //
    // Enable CPU int1 which is connected to CPU-Timer 0, CPU int13
    // which is connected to CPU-Timer 1, and CPU int 14, which is connected
    // to CPU-Timer 2:
    //
    EALLOW;  // This is needed to write to EALLOW protected registers
    IER |= M_INT1;    /* Enable if timer 0 Interrupt is used */
    //IER |= M_INT13;   /* Enable if timer 1 Interrupt is used - - DIRECT CPU */
    IER |= M_INT14;  /* Enable if timer 2 Interrupt is used - DIRECT CPU */
    IER |= M_INT9;  /* Enable if PIE INTx 9 Line is is used - IER = 0x100 - USED for SCI-A */
    IER |= M_INT12;  /* Enable if PIE INTx 12 Line is is used XINT3 */
 //   IER |= M_INT10;  /* Enable if PIE INTx 10 Line is is used ADCA4 */
    EDIS;

    //
    // Enable TINT0 in the PIE: Group 1 interrupt 7
    //
    EALLOW;
    PieCtrlRegs.PIECTRL.bit.ENPIE = 1;   // Enable the PIE block
    PieCtrlRegs.PIEIER1.bit.INTx7 = 1;     //TIMER 0 from PIEIER1
    PieCtrlRegs.PIEIER9.bit.INTx1 = 1;   // PIE Group 9, INT1   //SCIA_RX
    PieCtrlRegs.PIEIER9.bit.INTx2 = 1;   // PIE Group 9, INT2   //SCIA_TX
    PieCtrlRegs.PIEIER1.bit.INTx4 = 1;          // Enable PIE Group 1 INT4 (EXT INT 1)
    PieCtrlRegs.PIEIER1.bit.INTx5 = 1;          // Enable PIE Group 1 INT5 (EXT INT 2)
    PieCtrlRegs.PIEIER12.bit.INTx1 = 1;          // Enable PIE Group 12 INT1 (EXT INT 3)
   // PieCtrlRegs.PIEIER10.bit.INTx4 = 1;          // Enable PIE Group 12 INT1 (ADCA INT 1)
    PieCtrlRegs.PIEIER1.bit.INTx2 = 1;          // Enable PIE Group 2 INT1 (ADCB INT 1)
  //  PieCtrlRegs.PIEIER10.bit.INTx12 = 1;          // Enable PIE Group 12 INT1 (ADCC INT 1)
    EDIS;

    //
    // Interrupts that are used in this example are re-mapped to
    // ISR functions found within this file.
    //
    EALLOW;  // This is needed to write to EALLOW protected registers
    PieVectTable.TIMER0_INT = &cpu_timer0_isr;
    PieVectTable.TIMER2_INT = &cpu_timer2_isr;
    PieVectTable.SCIA_RX_INT = &sciaRxFifoIsr;
    PieVectTable.SCIA_TX_INT = &sciaTxFifoIsr;
    PieVectTable.XINT1_INT = &xint1_isr;
    PieVectTable.XINT2_INT = &xint2_isr;
    PieVectTable.XINT3_INT = &xint3_isr;
    //PieVectTable.ADCA4_INT = &adcA1ISR;     // Function for ADCA interrupt 1
    PieVectTable.ADCB1_INT = &adcB1ISR;     // Function for ADCB interrupt 1
   // PieVectTable.ADCC4_INT = &adcC1ISR;     // Function for ADCC interrupt 1
    EDIS;    // This is needed to disable write to EALLOW protected registers

    /* Init SCI module for RS485 UART operation */
    scia_Init();       // Initialize the SCI with FIFO

    /* Init External Interrupt on GPIO 49 and 50 */
    ExtInterrupt_Init();

    //
    // Step 6. User specific code, enable __interrupts:

    /* Configure GPIO35 as a GPIO output pin. It has Heart bit LED */

    EALLOW;
    GpioCtrlRegs.GPBMUX1.bit.GPIO40 = 0;
    GpioCtrlRegs.GPBDIR.bit.GPIO40 = 1;

    GpioCtrlRegs.GPBMUX1.bit.GPIO33 = 0;
    GpioCtrlRegs.GPBDIR.bit.GPIO33 = 1;
    EDIS;

    /* Initialize SFC SMD module */
    SfcSmd_Init();

    /* Init SPLL Module */
    Spll_Init();
    SpllReg_Init();


    //
    // Step 5. User specific code, enable interrupts:
    //



    //
    // Enable global Interrupts and higher priority real-time debug events:
    //
    EINT;  // Enable Global interrupt INTM
    ERTM;  // Enable Global realtime interrupt DBGM

    // Sync ePWM
    EALLOW;
    CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 1;
    EDIS;

    /* Reset faults on power up */
    SfcCompute_ResetFault();

    msg = "Modbus Active\0";
    RS485_DIRECTION_PIN_SET = 1; /* Set TX direction */
    TX_SBUF_A = 0x83;
    // scia_msg(msg);

    // Step 7. IDLE loop. Just sit and loop forever (optional):
    //
    while(1)
    {
        //SfcComp_InputDirectionDetection();
        SFC_Write_Data();
        Execute_PLC_commandc();

        // msg = "Deepak\n\0";
        // scia_msg(msg);
    }
}


//
// End of file
//

Fullscreen 1256.adc.c Download

//###########################################################################
//
// FILE:   adc.c
//
// TITLE:  ADC continuous self-triggering for F2837xS.
//
//! \addtogroup cpu01_example_list
//! <h1> ADC Continuous Triggering (adc_soc_continuous)</h1>
//!
//! This example sets up the ADC to convert continuously, achieving maximum
//! sampling rate.\n
//!
//! After the program runs, the memory will contain:
//!
//! - \b AdcaResults \b: A sequence of analog-to-digital conversion samples
//! from pin A0. The time between samples is the minimum possible based on the
//! ADC speed.
//
//**************************************************************************************

//
// Included Files
//
#include "F28x_Project.h"
//
// Function Prototypes
//
// Defines
//
#define RESULTS_BUFFER_SIZE 256 //buffer for storing conversion results
                                //(size must be multiple of 16)

//
// Globals
//
Uint16 AdcaResults[RESULTS_BUFFER_SIZE];
Uint16 resultsIndex;

/* ADC A interrupt */
__interrupt void adcA1ISR(void);
__interrupt void adcB1ISR(void);
__interrupt void adcC1ISR(void);

//
// ConfigureADC - Write ADC configurations and power up the ADC for both
//                ADC A and ADC B
//
void ADC_ConfigureADC(void)
{
    EALLOW;

    //
    // Setup VREF as internal
    //
    SetVREF(ADC_ADCA, ADC_EXTERNAL, ADC_VREF3P3);
    SetVREF(ADC_ADCB, ADC_EXTERNAL, ADC_VREF3P3);
    SetVREF(ADC_ADCC, ADC_EXTERNAL, ADC_VREF3P3);
    //
    //write configurations
    //
    AdcaRegs.ADCCTL2.bit.PRESCALE = 4; //set ADCCLK divider to /4
    AdcbRegs.ADCCTL2.bit.PRESCALE =4; //set ADCCLK divider to /4
    AdccRegs.ADCCTL2.bit.PRESCALE = 4; //set ADCCLK divider to /4
    //
    //Set pulse positions to late
    //
    AdcaRegs.ADCCTL1.bit.INTPULSEPOS = 1;
    AdcbRegs.ADCCTL1.bit.INTPULSEPOS = 1;
    AdccRegs.ADCCTL1.bit.INTPULSEPOS = 1;
    //
    //power up the ADC
    //
    AdcaRegs.ADCCTL1.bit.ADCPWDNZ = 1;
    AdcbRegs.ADCCTL1.bit.ADCPWDNZ = 1;
    AdccRegs.ADCCTL1.bit.ADCPWDNZ = 1;
    //
    //delay for 1ms to allow ADC time to power up
    //
    DELAY_US(1000);

    EDIS;
}

//
// SetupADCContinuous - setup the ADC to continuously convert on one channel
//
void ADC_SetupADCContinuous(void)
{
    Uint16 acqps;

    //
    // Determine minimum acquisition window (in SYSCLKS) based on resolution
    //
    acqps = 30; //

    EALLOW;
    //ADCA Regs - channels A0-A5
    AdcaRegs.ADCSOC0CTL.bit.CHSEL  = 0;  //SOC will convert on channel
    AdcaRegs.ADCSOC1CTL.bit.CHSEL  = 1;  //SOC will convert on channel
    AdcaRegs.ADCSOC2CTL.bit.CHSEL  = 2;  //SOC will convert on channel
    AdcaRegs.ADCSOC3CTL.bit.CHSEL  = 3;  //SOC will convert on channel
    AdcaRegs.ADCSOC4CTL.bit.CHSEL  = 4;  //SOC will convert on channel
    AdcaRegs.ADCSOC5CTL.bit.CHSEL  = 5;  //SOC will convert on channel
    AdcaRegs.ADCSOC6CTL.bit.CHSEL  = 6;  //SOC will convert on channel
    //    AdcaRegs.ADCSOC7CTL.bit.CHSEL  = 7;  //SOC will convert on channel
    AdcaRegs.ADCSOC8CTL.bit.CHSEL  = 8;  //SOC will convert on channel
    AdcaRegs.ADCSOC9CTL.bit.CHSEL  = 9;  //SOC will convert on channel

    //ADCB Regs - Channels B0 to B3
    AdcbRegs.ADCSOC0CTL.bit.CHSEL  = 0;  //SOC will convert on channel
    AdcbRegs.ADCSOC1CTL.bit.CHSEL  = 1;  //SOC will convert on channel
    //    AdcbRegs.ADCSOC2CTL.bit.CHSEL  = 2;  //SOC will convert on channel
    //    AdcbRegs.ADCSOC3CTL.bit.CHSEL  = 3;  //SOC will convert on channel
    AdcbRegs.ADCSOC4CTL.bit.CHSEL  = 4;  //SOC will convert on channel
    //    AdcbRegs.ADCSOC6CTL.bit.CHSEL  = 6;  //SOC will convert on channel
    //    AdcbRegs.ADCSOC7CTL.bit.CHSEL  = 7;  //SOC will convert on channel
    //    AdcbRegs.ADCSOC8CTL.bit.CHSEL  = 8;  //SOC will convert on channel

    //ADCC Regs - Channels C0 C2 C4
    AdccRegs.ADCSOC0CTL.bit.CHSEL  = 0;  //SOC will convert on channel
    AdccRegs.ADCSOC2CTL.bit.CHSEL  = 2;  //SOC will convert on channel
    //    AdccRegs.ADCSOC3CTL.bit.CHSEL  = 3;  //SOC will convert on channel
    AdccRegs.ADCSOC4CTL.bit.CHSEL  = 4;  //SOC will convert on channel

    AdcaRegs.ADCSOC0CTL.bit.ACQPS  = acqps;    //sample window is acqps +
    //1 SYSCLK cycles
    AdcaRegs.ADCSOC1CTL.bit.ACQPS  = acqps;    //sample window is acqps +
    //1 SYSCLK cycles
    AdcaRegs.ADCSOC2CTL.bit.ACQPS  = acqps;    //sample window is acqps +
    //1 SYSCLK cycles
    AdcaRegs.ADCSOC3CTL.bit.ACQPS  = acqps;    //sample window is acqps +
    //1 SYSCLK cycles
    AdcaRegs.ADCSOC4CTL.bit.ACQPS  = acqps;    //sample window is acqps +
    //1 SYSCLK cycles
    AdcaRegs.ADCSOC5CTL.bit.ACQPS  = acqps;    //sample window is acqps +
    //1 SYSCLK cycles
    AdcaRegs.ADCSOC6CTL.bit.ACQPS  = acqps;    //sample window is acqps +
    //1 SYSCLK cycles
    //    AdcaRegs.ADCSOC7CTL.bit.ACQPS  = acqps;    //sample window is acqps +
    //1 SYSCLK cycles
    AdcaRegs.ADCSOC8CTL.bit.ACQPS  = acqps;    //sample window is acqps +
    //1 SYSCLK cycles
    AdcaRegs.ADCSOC9CTL.bit.ACQPS  = acqps;    //sample window is acqps +
    //1 SYSCLK cycles

    AdcbRegs.ADCSOC0CTL.bit.ACQPS  = acqps;    //sample window is acqps +
    //1 SYSCLK cycles
    AdcbRegs.ADCSOC1CTL.bit.ACQPS  = acqps;    //sample window is acqps +
    //1 SYSCLK cycles
    //AdcbRegs.ADCSOC2CTL.bit.ACQPS  = acqps;    //sample window is acqps +
    //1 SYSCLK cycles
    // AdcbRegs.ADCSOC3CTL.bit.ACQPS  = acqps;    //sample window is acqps +
    //1 SYSCLK cycles
    AdcbRegs.ADCSOC4CTL.bit.ACQPS  = acqps;    //sample window is acqps +
    //1 SYSCLK cycles

    AdccRegs.ADCSOC0CTL.bit.ACQPS = acqps;    //sample window is acqps +
    //1 SYSCLK cycles
    AdccRegs.ADCSOC2CTL.bit.ACQPS = acqps;    //sample window is acqps +
    //1 SYSCLK cycles
    //    AdccRegs.ADCSOC3CTL.bit.ACQPS = acqps;    //sample window is acqps +
    //1 SYSCLK cycles
    AdccRegs.ADCSOC4CTL.bit.ACQPS = acqps;    //sample window is acqps +
    //1 SYSCLK cycles
    //ADCA Regs - channels A0-A5
    AdcaRegs.ADCSOC0CTL.bit.TRIGSEL  = 1;  //SOC will Trigger on CPU Timer 0 Interrupt
    AdcaRegs.ADCSOC1CTL.bit.TRIGSEL  = 1;
    AdcaRegs.ADCSOC2CTL.bit.TRIGSEL  = 1;
    AdcaRegs.ADCSOC3CTL.bit.TRIGSEL  = 1;
    AdcaRegs.ADCSOC4CTL.bit.TRIGSEL  = 1;
    AdcaRegs.ADCSOC5CTL.bit.TRIGSEL  = 1;
    AdcaRegs.ADCSOC6CTL.bit.TRIGSEL  = 1;
    //    AdcaRegs.ADCSOC7CTL.bit.TRIGSEL  = 1;
    AdcaRegs.ADCSOC8CTL.bit.TRIGSEL  = 1;
    AdcaRegs.ADCSOC9CTL.bit.TRIGSEL  = 1;

    //ADCB Regs - Channels B0 to B3
    AdcbRegs.ADCSOC0CTL.bit.TRIGSEL  = 1;  //SOC will Trigger on CPU Timer 0 Interrupt
    AdcbRegs.ADCSOC1CTL.bit.TRIGSEL  = 1;
    //    AdcbRegs.ADCSOC2CTL.bit.TRIGSEL  = 1;
    //    AdcbRegs.ADCSOC3CTL.bit.TRIGSEL  = 1;
    AdcbRegs.ADCSOC4CTL.bit.TRIGSEL  = 1;

    //ADCC Regs - Channels C2 to C4
    AdccRegs.ADCSOC0CTL.bit.TRIGSEL  = 1;  //SOC will Trigger on CPU Timer0 Interrupt
    AdccRegs.ADCSOC2CTL.bit.TRIGSEL  = 1;  //SOC will Trigger on CPU Timer0 Interrupt
    //    AdccRegs.ADCSOC3CTL.bit.TRIGSEL  = 1;
    AdccRegs.ADCSOC4CTL.bit.TRIGSEL  = 1;

//    AdcaRegs.ADCINTSEL1N2.bit.INT1SEL = 4; // End of SOC0 will set INT1 flag
 //   AdcaRegs.ADCINTSEL1N2.bit.INT1E = 1;   // Enable INT1 flag
 //   AdcaRegs.ADCINTFLGCLR.bit.ADCINT1 = 1; // Make sure INT1 flag is cleared
   AdcaRegs.ADCINTSEL1N2.bit.INT1CONT = 1;

    AdcbRegs.ADCINTSEL1N2.bit.INT1SEL = 4; // End of SOC0 will set INT1 flag
    AdcbRegs.ADCINTSEL1N2.bit.INT1E = 1;   // Enable INT1 flag
    AdcbRegs.ADCINTFLGCLR.bit.ADCINT1 = 1; // Make sure INT1 flag is cleared
    AdcbRegs.ADCINTSEL1N2.bit.INT1CONT = 1;

 //   AdccRegs.ADCINTSEL1N2.bit.INT1SEL = 4; // End of SOC0 will set INT1 flag
 //   AdccRegs.ADCINTSEL1N2.bit.INT1E = 1;   // Enable INT1 flag
 //   AdccRegs.ADCINTFLGCLR.bit.ADCINT1 = 1; // Make sure INT1 flag is cleared
    AdccRegs.ADCINTSEL1N2.bit.INT1CONT = 1;
    EDIS;
}

//
// adcA1ISR - ADC A Interrupt 1 ISR
//
__interrupt void adcA1ISR(void)
{

    //
    // Clear the interrupt flag
    //
    AdcaRegs.ADCINTFLGCLR.bit.ADCINT1 = 1;

    //
    // Check if overflow has occurred
    //
    if(1 == AdcaRegs.ADCINTOVF.bit.ADCINT1)
    {
        AdcaRegs.ADCINTOVFCLR.bit.ADCINT1 = 1; //clear INT1 overflow flag
        AdcaRegs.ADCINTFLGCLR.bit.ADCINT1 = 1; //clear INT1 flag
    }

    //
    // Acknowledge the interrupt
    //
    PieCtrlRegs.PIEACK.all = PIEACK_GROUP10;
}


//
// adcA1ISR - ADC A Interrupt 1 ISR
//
__interrupt void adcB1ISR(void)
{
    //
    // Clear the interrupt flag
    //
    AdcbRegs.ADCINTFLGCLR.bit.ADCINT1 = 1;

    //
    // Check if overflow has occurred
    //
    if(1 == AdcbRegs.ADCINTOVF.bit.ADCINT1)
    {
        AdcbRegs.ADCINTOVFCLR.bit.ADCINT1 = 1; //clear INT1 overflow flag
        AdcbRegs.ADCINTFLGCLR.bit.ADCINT1 = 1; //clear INT1 flag
    }

    //
    // Acknowledge the interrupt
    //
    PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;
}

//
// adcA1ISR - ADC A Interrupt 1 ISR
//
__interrupt void adcC1ISR(void)
{
    //
    // Clear the interrupt flag
    //
    AdccRegs.ADCINTFLGCLR.bit.ADCINT1 = 1;

    //
    // Check if overflow has occurred
    //
    if(1 == AdccRegs.ADCINTOVF.bit.ADCINT1)
    {
        AdccRegs.ADCINTOVFCLR.bit.ADCINT1 = 1; //clear INT1 overflow flag
        AdccRegs.ADCINTFLGCLR.bit.ADCINT1 = 1; //clear INT1 flag
    }

    //
    // Acknowledge the interrupt
    //
    PieCtrlRegs.PIEACK.all = PIEACK_GROUP10;
}

// End of file
//

Fullscreen sci_uart.c Download

/*
 * sci_uart.c
 *
 *  Created on: Nov 18, 2020
 *      Author: deepak.kadam
 */



#include "F28x_Project.h"
#include "sci_uart.h"
#include "modbus.h"




interrupt void sciaTxFifoIsr(void);
interrupt void sciaRxFifoIsr(void);
void reset_scia(void);

Uint16 rxdataA[8];    // Received data for SCI-A
/*
 * scia_fifo_init - Initialize the SCI with FIFO.
 * Test 1,SCIA  DLB, 8-bit word, baud rate 0x000F,default, 1 STOP bit, no parity
 */
void scia_Init()
{
    /* Set Direction port pin (GPIO) used in SCI-A */

    GPIO_SetupPinMux(43, GPIO_MUX_CPU1, 15); //Mux position 15
    GPIO_SetupPinOptions(43, GPIO_INPUT, GPIO_PUSHPULL);
    GPIO_SetupPinMux(42, GPIO_MUX_CPU1, 15); //Mux poistion 15
    GPIO_SetupPinOptions(42, GPIO_OUTPUT, GPIO_ASYNC);

    GPIO_SetupPinMux(67, GPIO_MUX_CPU1, 0);
    GPIO_SetupPinOptions(67, GPIO_OUTPUT, GPIO_PUSHPULL);

    /* Communication DIRECTION port pin used for 485 driver module */
    GpioCtrlRegs.GPBMUX1.bit.GPIO32 = 0;
    GpioCtrlRegs.GPBDIR.bit.GPIO32 = 1;

    /* SCI FIFO Init*/
   // SciaRegs.SCIFFTX.all = 0xE040;
   // SciaRegs.SCIFFRX.all = 0x2044;
   // SciaRegs.SCIFFCT.all = 0x0;

    //
    // Note: Clocks were turned on to the SCIA peripheral
    // in the InitSysCtrl() function
    //

    SciaRegs.SCICCR.all = 0x0007;   // 1 stop bit,  No loopback
    // No parity,8 char bits,
    // async mode, idle-line protocol
    SciaRegs.SCICTL1.all = 0x0003;  // enable TX, RX, internal SCICLK,
    // Disable RX ERR, SLEEP, TXWAKE
    SciaRegs.SCICTL2.all = 0x0003;
    SciaRegs.SCICTL2.bit.TXINTENA = 1;
    SciaRegs.SCICTL2.bit.RXBKINTENA = 1;

    //

    // @LSPCLK = 50 MHz (200 MHz SYSCLK) HBAUD = 0x02 and LBAUD = 0x8B.// SCIA at 9600 baud
    // @LSPCLK = 50 MHz (200 MHz SYSCLK) HBAUD = 0x01 and LBAUD = 0x45.// SCIA at 19200 baud
    // @LSPCLK = 50 MHz (200 MHz SYSCLK) HBAUD = 0x00 and LBAUD = 0xA3.// SCIA at 38400 baud

    //
    SciaRegs.SCIHBAUD.all = 0x0002;
    SciaRegs.SCILBAUD.all = 0x008B;

    SciaRegs.SCICTL1.all = 0x0023;  // Relinquish SCI from Reset

    SciaRegs.SCICTL1.bit.SWRESET    = 1;        // After a system reset, re-enable the SCI by writing a 1 to this bit.

 //   SciaRegs.SCIFFTX.bit.TXFIFORESET = 1;
 //   SciaRegs.SCIFFRX.bit.RXFIFORESET = 1;

    reset_scia();
}


//
// scia_xmit - Transmit a character from the SCI
//
void scia_xmit(int a)
{
    RS485_DIRECTION_PIN_SET = 1; /* Set TX direction */

    while (SciaRegs.SCIFFTX.bit.TXFFST != 0) {}
    SciaRegs.SCITXBUF.all =a;

    //RS485_DIRECTION_PIN_CLEAR =1;
}


//
// scia_msg - Transmit message via SCIA
//
void scia_msg(char * msg)
{
    int i;

    RS485_DIRECTION_PIN_SET = 1; /* Set TX direction */

    i = 0;
    while(msg[i] != '\0')
    {
        scia_xmit(msg[i]);
        i++;
    }

    //RS485_DIRECTION_PIN_CLEAR =1;
}


//
// sciaTxFifoIsr - SCIA Transmit FIFO ISR
//
interrupt void sciaTxFifoIsr(void)
{
    XmitSciaData();
//    SciaRegs.SCIFFTX.bit.TXFFINTCLR=1;   // Clear SCI Interrupt flag
    PieCtrlRegs.PIEACK.all=0x100;       // Issue PIE ACK
}

//
// sciaRxFifoIsr - SCIA Receive FIFO ISR
//
interrupt void sciaRxFifoIsr(void)
{
    ReceiveSciaData();

    SciaRegs.SCIFFRX.bit.RXFFOVRCLR=1;   // Clear Overflow flag
    SciaRegs.SCIFFRX.bit.RXFFINTCLR=1;   // Clear Interrupt flag

    PieCtrlRegs.PIEACK.all=0x100;       // Issue PIE ack
}


void reset_scia(void)
{
     if(SciaRegs.SCIRXST.bit.RXERROR==1)                     /* Error flag(s) set */
     {
         SciaRegs.SCICTL1.bit.SWRESET    = 0;                 /* Writing a 0 to this bit initializes the SCI state machines and operating flags (registers SCICTL2 and
         SCIRXST) to the reset condition */
     }
     gSerialBytesRxCounter                        = 0;                 // Buffer length
//     RS485_RX_ENABLE_A                   = 1;                 // RS 485 receive enable
     SciaRegs.SCICTL1.bit.SWRESET        = 1;                 /* After a system reset, re-enable the SCI by writing a 1 to this bit.*/
     PieCtrlRegs.PIEACK.all              = PIEACK_GROUP9;     /* Reinitialize for next Sci */
 }

over 4 years ago

0 Vasudha Bhadoria over 4 years ago

TI__Genius 10845 points

Hi,

I am looking into this query and will get back shortly.

Thanks
Vasudha

0 Vasudha Bhadoria over 4 years ago

TI__Genius 10845 points

Hi,

Can you provide more details on the issue? There are multiple files attached here in the above post. Are ADC results read inside Timer ISR or ADC ISR in the application code. If read in timer ISR, check if the conversion is complete before reading the ADC Results.

Thanks
Vasudha

0 Deepak Kadam over 4 years ago in reply to Vasudha Bhadoria

Prodigy 20 points

Hi,

I am getting ADC EOC interrupts regularly but values in ADCRESULTREG are not getting updated. Its stuck.

0 Vasudha Bhadoria over 4 years ago in reply to Deepak Kadam

TI__Genius 10845 points

Hi,

Were you able to resolve the issue? I think the ADC result is not getting read at the right time in the code leading to this issue. Is the result read in Timer ISR or the ADC ISR? If read in Timer ISR, is the interrupt flag checked before reading the result?

Thanks
Vasudha

0 Deepak Kadam over 4 years ago in reply to Vasudha Bhadoria

Prodigy 20 points

Hi Vasudha,

Issue is not resolved yet. I am using Timer0 SOC trigger to start conversion. I am using ADC EOC interrupt to read the ASC result register.

I have uploaded source files earlier in case you would like to go through.

Regards,

Deepak

0 Vasudha Bhadoria over 4 years ago in reply to Deepak Kadam

TI__Genius 10845 points

Hi,

Just to rule out issues other than the application code, can you check if you are getting valid ADC output while executing any of the ADC example available under C2000Ware. I can assist on the issues related to code once we ruleout issues related to hardware setup.

Thanks
Vasudha

0 Deepak Kadam over 4 years ago in reply to Vasudha Bhadoria

Prodigy 20 points

Hi,

Yes, I am able to get adc results on using c2000ware examples for ADC (using epwm SOC too). I have tried this on 49C LaunchXL as well as on my custom board also.

I also modified C2000ware examples to read multiple ADC channels using EPWM1 SOC and it works perfectly on both boards.

Only my code wont work. The main difference being SOC in my code is Timer0 Trigger.

Right now I am using this workaround of EPWM SOC, which is working for me.

Still I want to understand what wrong I am doing in using Timer0 SOC.

Regards,

Deepak

0 Vasudha Bhadoria over 4 years ago in reply to Deepak Kadam

TI__Genius 10845 points

Hi,

Good to know that you have a workaround. One issue could be timer trigger getting generated before the result is read leading to incorrect data being read. Can you check the time taken in the ISR code being used in the application?

Thanks
Vasudha

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LAUNCHXL-F280049C: ADCB1 interrupt coming but ADC results are not updated in result register. ADC values stuck to single value of 127