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TMS320F280025C: Significance of smaller acquisition window when the sampling rate of ADC is lower

Duman Demir
Prodigy 132 points
Part Number: TMS320F280025C

I am using an ePWM SOC to trigger ADC continuously at  5kHz. So the ADC will take only one sample in a period of 200usec.

If acquisition window is set to 75ns, then ADC sample and hold circuit will be idle for next 199.925us. 

If acquisition window is set to 1us, then ADC will not take sample for next 199us.

Would there be any effect on performance of the system if I set acquisition window significantly greater than 75ns (minimum acquisition window for the ADC)? Since with lower acquisition window the bandwidth requirement of the opamp in  ADC driving circuit is also reduced.

An implication I think would be that if I set acquisition window significantly higher than 75ns, then there is a chance that the accurate value of signal is not captured as it can be changed to a new value during the acquisition window duration, right? However, since the sampling rate is set to a value of 5kHz, the chances of missing the signal information are far greater when ADC S/H is idle than during the acquisition window. So, the conclusion is that the acquisition window could be set to a significantly higher value but it must be greater than minimum value as specified in datasheet and it must be less than the sampling time period (200us in the case mentioned). Is this conclusion right?

Note: We expect the signal to be converted will not have variations at much higher rates.

  • +1
    TI__Mastermind 37950 points

    Hi Duman,

    What kind of signal are you sampling?  If it is steady-state DC, then S/H would not matter significantly.  If it is dynamic, how fast does the signal change?  The sampling capacitor in the ADC gets charged by the input signal through the sample switch for the duration specified by acquisition.  For instance, in your application, S/H is set to 75ns.  In an ideal situation for continuous conversion, that means that if a 1MHz signal (1us period) is captured by the ADC, there would be about 1us/75ns samples that can be captured, or around 13 samples.  If signal is 500Hz (2ms period), you can potentially capture ~26,000 samples.  If you increase S/H, the number of samples will decrease.  Then there is the sampling frequency and for the application example above, EPWM is used to trigger the sampling at 5kHz.  This rate is probably chosen to coincide with the input signal

    Sampling time (or ACQPS) is largely dictated by the impedance present on the input circuit.  ADC sampling is basically having the internal sampling capacitor charged to the acceptable level through the  low pass filter representation of the RCs associated with your input circuit.  In general, yes, you can increase the S/H time to get a more stable signal but have to consider the type of signal being sampled, frequency of sampling and more importantly the impedances around the input circuit of the pin used to sample.  There is a helpful application note that you can refer to about input circuits and how it affects sampling at https://www.ti.com/lit/an/spract6/spract6.pdf.  

    Best regards,

    Joseph

  • 0 in reply to Joseph Casuga
    Prodigy 132 points

    Thank you Joseph for a comprehensive answer. I have gone through the reference you shared. So the conclusion is that if we are sampling DC signal then we can set acquisition time to a large value which allows us to use any available opamp with smaller bandwidth in the ADC input driver circuit design as presented in spract6.