The code from sci.h is shown:
static inline void
SCI_writeCharBlockingFIFO(uint32_t base, uint16_t data)
{
//
// Check the arguments.
//
ASSERT(SCI_isBaseValid(base));
//
// Wait until space is available in the transmit FIFO.
//
while(SCI_getTxFIFOStatus(base) == SCI_FIFO_TX15)
{
}
//
// Send a char.
//
HWREGH(base + SCI_O_TXBUF) = data;
}
However the waiting condition should be:
while(SCI_getTxFIFOStatus(base) == SCI_FIFO_TX16)
This can cause an excessive amount of time spent in the interrupt in the following case:
void init()
{
...
SCI_enableInterrupt(BaseAddress, (SCI_INT_RXFF | SCI_INT_TXFF));
SCI_setFIFOInterruptLevel(BaseAddress, SCI_FIFO_TX1, SCI_FIFO_RX1);
...
}
void tx_isr()
{
do
{
//let SCI TX Fifo push out to SXITXBUF
if (txCBuff.isEmpty())
{
SCI_disableInterrupt(BaseAddress,SCI_INT_TXFF);
break;
}
SCI_writeCharBlockingFIFO(BaseAddress,txCBuff.pop());
} while(SCI_getTxFIFOStatus(BaseAddress) < SCI_FIFO_TX16);
...
}
In the above example, the device interrupt will hang waiting for the TX FIFO to drop below 15 whenever the 16th byte is attempted to be added.
The TI response in the previous thread (see related, 10 months ago), stated it would be fixed in the next release. It was not.
