TMS320F280049: how many CPU cycles required to enter the CLA task?

Aki,

The CLA experts are OOO until Monday, but I'll try to answer based on what I know of the C28x core.  Since C28x triggers the CLA with a IACK ## instruction, I believe this should occur in the execute phase (E) phase of the C28x  instruction pipeline, which would be 7 cycles after the instruction was fetched from memory.  I'm assuming that if the CLA is idle the start of the task would be on the next clock cycle of the CLA, so 8 clocks after the IACK was executed from memory.

I will add, that if the instruction does not reach the D2 phase(4th step of the pipeline) it could get discarded on an interrupt.  The IACK would eventually get started, but only after the ISR is complete, so there would be a bigger delay to the CLA task(since it could have been running in parallel to the C28x).

I'll let the experts give their comment on Monday, in case my interpretation is incorrect.

Best,

Matthew