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Timer0, SCIA, and SCIB Interrupts



Hello,

My Timer0, SCIA, and SCIB do not work consistanly.  Sometime, the timer worked but not the SCIA nor SCIB receiver, and sometime the receivers of both SCIA and SCIB worked very well but not the timer.  However, all Timer0, SCIA, and SCIB worked very well with the same code.  Would you please take a look at the following code to see if I initilalized and enabled Timer0, SCIA, SCIB correctly?  I basically used the LEDBlink example and added the SCIA and SCIAB initialization codes in.  Thank you very much.

void main(void)
{

//  Step 1. Initialize System Control:
//  PLL, WatchDog, enable Peripheral Clocks
    InitSysCtrl();

//  Step 2. Initalize GPIO:
    InitSciGpio();
   
//  Step 3. Clear all interrupts and initialize PIE vector table:
//  Disable CPU interrupts
    DINT;

//  Initialize PIE control registers to their default state.
    InitPieCtrl();

//  Disable CPU interrupts and clear all CPU interrupt flags:
    IER = 0x0000;
    IFR = 0x0000;

//  Initialize the PIE vector table with pointers to the shell Interrupt
//  Service Routines (ISR).
//  This will populate the entire table, even if the interrupt
    InitPieVectTable();

//  Interrupts that are used in this example are re-mapped to
//  ISR functions found within this file.
    EALLOW; // This is needed to write to EALLOW protected registers
    PieVectTable.SCIRXINTA = &sciaRxFifoIsr;
    PieVectTable.SCIRXINTB = &scibRxFifoIsr;
    PieVectTable.TINT0 = &cpu_timer0_isr;
    EDIS;
   // This is needed to disable write to EALLOW protected registers
 
//  Step 4. Initialize all the Device Peripherals:
    scia_fifo_init();                // Init SCI-A
    scib_fifo_init();                // Init SCI-B
    InitCpuTimers();              // initialize the Cpu Timers

//  Step 5. User specific code, enable interrupts:

    ConfigCpuTimer(&CpuTimer0, 150, 500000);      // 0.5 second timer


// To ensure precise timing, use write-only instructions to write to the entire register. Therefore, if any
// of the configuration bits are changed in ConfigCpuTimer and InitCpuTimers (in DSP2833x_CpuTimers.h), the
// below settings must also be updated.

    CpuTimer0Regs.TCR.all = 0x4001; // Use write-only instruction to set TSS bit = 0

// Configure GPIO32 as a GPIO output pin
    EALLOW;
    GpioCtrlRegs.GPBMUX1.bit.GPIO34 = 0;
    GpioCtrlRegs.GPBDIR.bit.GPIO34 = 1;
    EDIS;

// Enable CPU int1 which is connected to CPU-Timer 0
     IER = 0x101 ; // Enable CPU INT

// Enable TINT0 in the PIE: Group 1 interrupt 7
    PieCtrlRegs.PIEIER1.bit.INTx7 = 1;


//  Enable interrupts required for this example
    PieCtrlRegs.PIECTRL.bit.ENPIE = 1;         // Enable the PIE block
    PieCtrlRegs.PIEIER9.bit.INTx1 = 1;           // PIE Group 9, int1
    PieCtrlRegs.PIEIER9.bit.INTx3 = 1;           // PIE Group 9, INT3


    EINT;
    ERTM;
   // Enable Global realtime interrupt DBGM

//  Step 6. IDLE loop. Just sit and loop forever (optional):
 for(;;){}
}

  • For further information to help myself and others possibly diagnose your problem can you post the following code:

    The functions:

       scia_fifo_init();                // Init SCI-A
        scib_fifo_init();                // Init SCI-B
        InitCpuTimers();              // initialize the Cpu Timers

    sciaRxFifoIsr();

    scibRxFifoIsr();

    cpu_timer0_isr();

    Also check InitPeripheralClocks() in DSP2833x_SysCtrl.c to ensure all 3 peripherals have their clocks.  Since DSP2833x_SysCtrl.c is usually a shared file, one can make the mistake of changing it for one project and forgetting the change.

    Hopefully that should be enough information to find the problem.


    Tim

  • Thanks for your reply, and yes here are the codes for these functions.  Thanks for your helps.

    void scia_fifo_init(void)
    {
        SciaRegs.SCICCR.bit.SCICHAR = 7;      //  1 stop bit,  No loopback
                                             //  No parity,8 char bits,
        SciaRegs.SCICTL1.all =0x0000;         // disenable TX, RX, internal SCICLK,
                                             //  Disable RX ERR, SLEEP, TXWAKE
        SciaRegs.SCICCR.bit.LOOPBKENA = 0;       //  Disable loop back test mode
                                             //  async mode, idle-line protocol
                   // Issue software reset
        SciaRegs.SCICTL2.bit.TXINTENA = 0;      // Enable TXRDY interrupt
        SciaRegs.SCICTL2.bit.RXBKINTENA = 1;     // Enable RXRYD/BRKDT interrupt

        SciaRegs.SCIHBAUD = 0x0001;        // (if 30MHZ use 1E7)
        SciaRegs.SCILBAUD = 0x00E7;        // (if 20MHz use 144)
                   
        SciaRegs.SCIFFTX.bit.SCIRST = 1;      // Resume SCI FIFO TX/RX
        SciaRegs.SCIFFTX.bit.SCIFFENA = 1;      // Enable SCI FIFO enhancement

        SciaRegs.SCIFFRX.bit.RXFFIENA = 1;      // RX FIFO interrupt based on RXFFIVL match
        SciaRegs.SCIFFRX.bit.RXFFIL = 1;      // RX FIFO interrupt leval bits
     
        SciaRegs.SCIFFCT.all = 0x0000;       // FIFO delay

        SciaRegs.SCICTL1.bit.RXENA = 1;       // Enable RX SCI and send character to SCIRXEMUa nd SCIRXBUF
        SciaRegs.SCICTL1.bit.TXENA = 1;       // TX enable

        SciaRegs.SCICTL1.bit.SWRESET = 1;        //  Re-eable SCI from Reset above

        SciaRegs.SCIFFTX.bit.TXFIFOXRESET = 1;     // Re-enable TX FIFO operation 
        SciaRegs.SCIFFRX.bit.RXFIFORESET = 1;     // Re-enable RX FIFO operation
    }

    void scib_fifo_init(void)
    {
        ScibRegs.SCICCR.bit.SCICHAR = 7;         //  1 stop bit,  No loopback
                                              //  No parity,8 char bits,
                                              //  async mode, idle-line protocol
        ScibRegs.SCICTL1.all = 0x0000;         // SCI software reset

        ScibRegs.SCICCR.bit.LOOPBKENA = 0;       //  Disable loop back test mode

        ScibRegs.SCICTL2.bit.TXINTENA = 0;      // Enable TXRDY interrupt
        ScibRegs.SCICTL2.bit.RXBKINTENA = 1;     // Enable RXRYD/BRKDT interrupt

        ScibRegs.SCIHBAUD = 0x0001;        // (if 30MHZ use 1E7)
        ScibRegs.SCILBAUD = 0x00E7;        // (if 20MHz use 144)

        ScibRegs.SCIFFTX.bit.SCIRST = 1;      // Resume SCI FIFO TX/RX
        ScibRegs.SCIFFTX.bit.SCIFFENA = 1;      // Enable SCI FIFO enhancement
       
        ScibRegs.SCIFFRX.bit.RXFFIENA = 1;      // RX FIFO interrupt based on RXFFIVL match
        ScibRegs.SCIFFRX.bit.RXFFIL = 1;      // RX FIFO interrupt level bits

        ScibRegs.SCIFFCT.all = 0x0000;       // FIFO delay

        ScibRegs.SCICTL1.bit.RXENA = 1;       // Enable RX SCI and send character to SCIRXEMUa nd SCIRXBUF
        ScibRegs.SCICTL1.bit.TXENA = 1;       // TX enable

        ScibRegs.SCICTL1.bit.SWRESET = 1;        //  Re-eable SCI from Reset above
                   
        ScibRegs.SCIFFTX.bit.TXFIFOXRESET = 1;     // Re-enable TX FIFO operation 
        ScibRegs.SCIFFRX.bit.RXFIFORESET = 1;     // Re-enable RX FIFO operation
    }

    void InitCpuTimers(void)
    {
        // CPU Timer 0
        // Initialize address pointers to respective timer registers:
        CpuTimer0.RegsAddr = &CpuTimer0Regs;
        // Initialize timer period to maximum:
        CpuTimer0Regs.PRD.all  = 0xFFFFFFFF;
        // Initialize pre-scale counter to divide by 1 (SYSCLKOUT):
        CpuTimer0Regs.TPR.all  = 0;
        CpuTimer0Regs.TPRH.all = 0;
        // Make sure timer is stopped:
        CpuTimer0Regs.TCR.bit.TSS = 1;
        // Reload all counter register with period value:
        CpuTimer0Regs.TCR.bit.TRB = 1;
        // Reset interrupt counters:
        CpuTimer0.InterruptCount = 0;

    }

    interrupt void sciaRxFifoIsr(void)
    {
        SciaRegs.SCIFFRX.bit.RXFIFORESET = 0;     // Reset FIFO pointer to zero
        SciaRegs.SCIFFRX.bit.RXFIFORESET = 1;     // Re-enable RX FIFO operation

        SciaRegs.SCIFFRX.bit.RXFFOVRCLR = 1;        // Clear Overflow flag
        SciaRegs.SCIFFRX.bit.RXFFINTCLR = 1;        // Clear Interrupt flag

        PieCtrlRegs.PIEACK.all |= 0x100;            // Issue PIE ack
    }

    ///////////////////////////////////////////////////////////////////////////
    ////////////////////// SCIB Port Interrupt  ///////////////////////////////
    ///////////////////////////////////////////////////////////////////////////

    interrupt void scibRxFifoIsr(void)
    {
        ScibRegs.SCIFFRX.bit.RXFIFORESET = 0;     // Reset FIFO pointer to zero
        ScibRegs.SCIFFRX.bit.RXFIFORESET = 1;     // Re-enable RX FIFO operation

        ScibRegs.SCIFFRX.bit.RXFFOVRCLR = 1;       // Clear Overflow flag
        ScibRegs.SCIFFRX.bit.RXFFINTCLR = 1;      // Clear Interrupt flag

        PieCtrlRegs.PIEACK.all |= 0x100;        // Issue PIE ack
    }

    ///////////////////////////////////////////////////////////////////////////
    //////////////////////   Timer 0 Interrupt  ///////////////////////////////
    ///////////////////////////////////////////////////////////////////////////

    interrupt void cpu_timer0_isr(void)
    {
        CpuTimer0.InterruptCount++;
        GpioDataRegs.GPBTOGGLE.bit.GPIO34 = 1;      // Toggle GPIO32 once per 500 milliseconds

        // Acknowledge this interrupt to receive more interrupts from group 1
        PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;
    }

  • Unfortunately I can't see anything in this code which would be causing your issues.  The initializations all seem good.  I can't see any obvious interactions.

    I would suggest trying them two at a time (SCIA+B, SCIA+Timer, SCIB+Timer) and see if you can find out anything more about when exactly the issue strikes.

    Sorry I couldn't help further,

    Tim