Reference design when using on-chip VREG of F2802X

Knighty

Hello All,

We designed F2802X and plan to use on-chip VREG but concern about glitch during power up, understand datasheet recommended VDD pin has reach 0.7V before VDDIO reach 0.7V so can I have reference circuit design when we use on-chip VREG?

Thanks

over 15 years ago

0 David Foley over 15 years ago

TI__Expert 8500 points

NT,

This requirement exists on some earlier devices, but it does not exist on the Piccolo class devices (of which the F2802x is a part of). Are you sure you are looking at the correct datasheet? There should be no power sequencing requirement to keep the I/O from glitching during power on this device.

Regards,
Dave Foley

0 Knighty over 15 years ago in reply to David Foley

Intellectual 380 points

Dave,

datasheet(page 8) stage below. could you help to clearify when I used on-chip VREG, I need 1.8V external supply(core) to prevent glitch during turn on with no sequencing require?

Thanks,

0 David Foley over 15 years ago in reply to Knighty

TI__Expert 8500 points

NT,

Yes, on those pins. I forgot about them. On the majority of pins you do not have this requirement though. Can you not move the critical functions to other pins?

Regards,
Dave Foley

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Reference design when using on-chip VREG of F2802X