Hi, support team
My customer has the questions as follow:
I have an issue where occasional from power on the microprocessor Sci-A RX interrupt fails to work properly. On most power up cycles, the microprocessor will work fine, but occasional (one in every five or so) will fail. To rule out power sequencing rules, I've been able to replicate the issue on the EZDSP eval board for the F2812 and can also replicate the issue using CPU RESET in TI Code Composer on debugger. The SCI-A is setup as a UART running at 38,400 baud with Odd Parity, FIFO enable, RX and TX interrupts are set.
When the failure occurs, the state of the system is as follows.
PIE confirms SCI-A RX and TX are enabled in IER #9. IFR #9 always reads 0.
SCI-A RX FIFO Status shows data is present, FIFO level is full at 16 and overrun is set. Additionally, RXINT is active (1).
In attempt to kick start, I forcefully drained the FIFO and acknowledge the interrupt as would in the ISR. After completing, I can confirm (using a GPIO on a scope) the RXINT is reset. But after new data received, PIE fails to set the interrupt.
This condition is permanent until I reset power. Any ideas what is going on? I do not understand how the PIE is apparantly frozen or ignoring SCI-A RXINT? A timer interrupt in the system is behaving correctly during this time. Recommended fixes?
I can provide you snippet of code showing PIE, SCI-A initialization as well as a ISR routines for troubleshooting if desired.
Thanks so much.
Best regards,
Yuki
