Hi,
I have a question about CLB clock settings. From other threads, I understand that CLB Tile and Register clocks are created by dividing SYSCLK.
However, I can't find the datail of CLB clock in the DS and TRM of F280049C.
Where is the CLB Clock system diagram and register information?
For example, if I want to set it to 50MHz, I don't know what to set.
Regards,
Rei
