I was reading "F2837xD_Microcontroller_MDW_2-0.pdf" section "IPC Data Transfer: Basic Data Transfer".
Here it is described that:
- CPU1 will write Data to C1toC2 message RAM and set a flag
- CPU2 will check if the flag is set and if true it will read the data from C1toC2 message RAM
I've written sample program without the above flagging mechanism, the program is as below:
- CPU1 keeps on writing some data to C1toC2 message RAM (without setting any flags)
- CPU2 keeps on reading data from C1toC2 message RAM (without checking any flags)
Idea is to let the CPU2 read the latest data in C1toC2 message RAM whenever it is required.. this works for the sample program.
My question is will this create any problem such as deadlock? Since the two cores are not running in sync.. there could be chances that when CPU1 try to write data to shared RAM, at the same time CPU2 might try to read data from the same shared memory location.
