TMS320F280049C-Q1: TMS320F280049C-Q1

Hi Akshay,

There are bits and fields in ADCCTL1 register that you can poll like ADCBSY and ADCBSYCHN and register ADCSOCFLG1.  These would give indication whether the ADC is converting (busy), what was the last SOC that has converted or is currently converting or which SOC received a trigger.  You could potentially write a routine to poll these registers as to when trigger to start conversion has been received.  There is a free running 12-bit clock, ADCCOUNTER,  that counts with respect to SYSCLK, which is the same clock that gates conversions (S/H, EOC,  quantization  - refer to the ADC timing diagrams in TRM chapter 13.12).  There is an accompanying table with the timing diagrams that indicate how many SYSCLK cycles it takes, after SOC S+H has expired when tEOC and tLAT (latency time for quantization - digital value will be available in ADC results registers) events will have occurred.  The table would have different values for tEOC and tLAT depending on prescalers used.

There will be caveats when using the above registers:  Register polling will have CPU overhead and that the free running counter will overflow after 4095 SYSCLK counts and would restart again so you would need to take care of this.  The CPU overhead in reading the SOC start/trigger and ADC counter will be significant and might end up missing the tEOC/tLAT event and could lead to incorrect results being read from the ADC results register.  Have not tried this method and we do not have examples for this as well but is is something that you can potentially try and experiment with.

Best regards,

Joseph