C2000WARE: Dead-band module not working properly, gate drive signals are overlapping

Hi Joel,

Since you are using the high resolution PWM mode, when CTRMODE is configured for up count mode, the deadband module is not supported. You'll have to switch CTRMODE to be UP/DOWN count mode. 

We are working towards updating our Technical Reference Manual to include this note.

Best Regards,

Marlyn

Hi Marlyn,

Thanks very much for this, I'll get straight on to programming that and see if it makes any difference. 

However, I still have the same issue of overlap in my fourth PWM module, EPWM4, which does not use HRPWM mode. I *think* I have this set up for AHC, so not sure why I am seeing the overlap.

// Resonant LCC PWM Module
void InitEPwm4(void)
{
// Setup time-base
EPwm4Regs.TBCTL.bit.CTRMODE = 0; // Up-count Mode
EPwm4Regs.TBPRD = RES_PERIOD_MIN; // Initialise TBPRD with the highest frequency to start
EPwm4Regs.TBCTL.bit.PHSEN = 0; // Disable phase loading
EPwm4Regs.TBPHS.bit.TBPHS = 0x0000; // Phase is 0
EPwm4Regs.TBCTR = 0x0000; // Clear counter

// Set TBCLK = EPWMCLK = 100MHz
EPwm4Regs.TBCTL.bit.HSPCLKDIV = 0; // Clock ratio to SYSCLKOUT
EPwm4Regs.TBCTL.bit.CLKDIV = 0; //
EPwm4Regs.TBCTL.bit.SYNCOSEL = 0x0; // Disable synchronised output (??)

// Set initial modulation
EPwm4Regs.CMPA.bit.CMPA = RES_PERIOD_MIN/2; // Set initial compare A value
// EPwm4Regs.CMPB.bit.CMPB = RES_PERIOD_MIN/2;

// Set actions
EPwm4Regs.AQCTLA.bit.CAU = 0x1; // Force PWMA low on count up when TBCTR = CMPA
EPwm4Regs.AQCTLA.bit.ZRO = 0x2; // When TBCTR = ZRO, force PWMA high

EPwm4Regs.DBCTL.bit.OUT_MODE = 3; // DB full enable
EPwm4Regs.DBCTL.bit.POLSEL = 2; // Active high complementary (AHC)
EPwm4Regs.DBFED.bit.DBFED = RES_PERIOD_MIN*0.05; // Set initial dead-time for resonant module
EPwm4Regs.DBRED.bit.DBRED = RES_PERIOD_MIN*0.05; // Set initial dead-time for resonant module

EALLOW;
// Digital Compare (DC) Submodule
// Generate DCAH signal from Trip Combination Input
EPwm4Regs.DCTRIPSEL.bit.DCAHCOMPSEL = 15; // OR together all Trip combinations selected by DCALTRIPSEL Registers -> DCAH
EPwm4Regs.DCTRIPSEL.bit.DCBHCOMPSEL = 15; // OR together all Trip combinations selected by DCALTRIPSEL Registers -> DCBH

// DCAH/DCAEVT1/2 are used for one-shot trip faults
// DCBH/DCBEVT1/2 are used for cycle-by-cycle faults
// Individually select which trip signals are passed into the block to be ORed together
EPwm4Regs.DCAHTRIPSEL.bit.TRIPINPUT5 = 1; // Input Over Voltage Trip One-Shot Fault
EPwm4Regs.DCAHTRIPSEL.bit.TRIPINPUT8 = 1; // Collector Over Voltage Trip One-Shot Fault
EPwm4Regs.DCBHTRIPSEL.bit.TRIPINPUT10 = 1; // Resonant Over Current Trip Cycle-by-Cycle Fault

// Event A Action Qualifier block
// Generate DCAEVT1/DCBEVT1 trip events according to DCAH and DCBH
// Only EVT1 can be used for OST, and EVT2 for CBC
// Need to enable both A and B of these registers to trigger both the PWMx outputs
EPwm4Regs.TZDCSEL.bit.DCAEVT1 = 2; // DCAEVT1: DCAH = high, DCAL = don't care
EPwm4Regs.TZDCSEL.bit.DCAEVT2 = 2; // DCAEVT2: DCAH = high, DCAL = don't care
EPwm4Regs.TZDCSEL.bit.DCBEVT1 = 2; // DCBEVT1: DCBH = high, DCBL = don't care
EPwm4Regs.TZDCSEL.bit.DCBEVT2 = 2; // DCBEVT2: DCBH = high, DCBL = don't care

// Event Triggering block - Generate DCAEVT1.force and DCBEVT1.force signals (One Shot Source)
EPwm4Regs.DCACTL.bit.EVT1SRCSEL = 0; // Select DCAEVT1 as input signal
EPwm4Regs.DCACTL.bit.EVT1FRCSYNCSEL = 1; // Select Asynchronous
EPwm4Regs.TZFRC.bit.DCAEVT1 = 0; // Enable DCAEVT1.force output signal
EPwm4Regs.DCBCTL.bit.EVT1SRCSEL = 0; // Select DCBEVT1 as input signal
EPwm4Regs.DCBCTL.bit.EVT1FRCSYNCSEL = 1; // Select Asynchronous
EPwm4Regs.TZFRC.bit.DCBEVT1 = 0; // Enable DCBEVT1.force output signal

// Event Triggering block - Generated DCAEVT2.force and DCBEVT2.force signals (Cycle-by-Cycle Source)
EPwm4Regs.DCACTL.bit.EVT2SRCSEL = 0; // Select DCAEVT2 as input signal
EPwm4Regs.DCACTL.bit.EVT2FRCSYNCSEL = 1; // Select Asynchronous
EPwm4Regs.TZFRC.bit.DCAEVT2 = 0; // Enable DCAEVT2.force output signal
EPwm4Regs.DCBCTL.bit.EVT2SRCSEL = 0; // Select DCBEVT2 as input signal
EPwm4Regs.DCBCTL.bit.EVT2FRCSYNCSEL = 1; // Select Asynchronous
EPwm4Regs.TZFRC.bit.DCBEVT2 = 0; // Enable DCBEVT2.force output signal

// Trip Zone Submodule - Trip Logic block
// Using only TZCTL and EVT1
EPwm4Regs.TZCTL2.bit.ETZE = 0; // Use only TZCTL register, disable TSCTL2

EPwm4Regs.TZCTL.bit.DCAEVT1 = 0x10; // On trip, force EPWM4A to a LOW state
EPwm4Regs.TZCTL.bit.DCBEVT1 = 0x10; // On trip, force EPWM4B to a LOW state
EPwm4Regs.TZCTL.bit.DCAEVT2 = 0x10; // On trip, force EPWM4A to a LOW state
EPwm4Regs.TZCTL.bit.DCBEVT2 = 0x10; // On trip, force EPWM4B to a LOW state
EPwm4Regs.TZCTL.bit.TZA = 0x10; // On trip, force EPWM4A to a LOW state
EPwm4Regs.TZCTL.bit.TZB = 0x10; // On trip, force EPWM4B to a LOW state

// Trip-Zone Submodule - select OSHT and CBC sources
EPwm4Regs.TZSEL.bit.DCAEVT1 = 1; // Enable DCAEVT1 as one-shot-trip source for this ePWM module
EPwm4Regs.TZSEL.bit.DCBEVT1 = 1; // Enable DCBEVT1 as one-shot trip source for this ePWM module
EPwm4Regs.TZSEL.bit.DCAEVT2 = 1; // Enable DCAEVT2 as a CBC trip source for this ePWM module
EPwm4Regs.TZSEL.bit.DCBEVT2 = 1; // Enable DCBEVT2 as a CBC trip source for this ePWM module

//EPwm4Regs.TZFRC.bit.OST = 0x01; // Force trip to disable PWM outputs
//EPwm4Regs.TZFRC.bit.CBC = 0x01; // Force cycle-by-cycle trip to disable PWM outputs

// May insert code which either waits a delay time before clearing the one-shot fault, or something along those lines
EDIS;

// Set up ADC trigger pulse to ADC SOCA (ADCAINT1)
EPwm4Regs.ETSEL.bit.SOCAEN = 0; // Disable SOCA on A group
EPwm4Regs.ETSEL.bit.SOCASEL = 2; // Select SOCA on period match
EPwm4Regs.ETSEL.bit.SOCAEN = 1; // Enable SOCA
EPwm4Regs.ETPS.bit.SOCAPRD = 1; // Generate pulse on 1st event
}

Let me know if you've any more ideas/thoughts.

Best, 
Joel

Hi Marlyn

Just read the following from a 3 years ago blog post: 

The following are some general guidelines. There are likely many other choices that one can make for a particular power stage/application that may provide benefits to that particular use case.

1. Up and down count PWM operations give 2x the number of cycle counts than up-down count operation at the same PWM frequency.
   1. This means you can achieve higher resolution.

2. Symmetric (up-down count) PWM methods are often used when low harmonic distortion is desired.
3. HRPWM (High-Resolution PWM) operation on C2000 devices imposes some duty cycle value restrictions.
   1. For up or down count modes, without high resolution period: A loss of 3 system clock duty cycle steps in one PWM period.
   2. For up count mode, with high-resolution period: A loss of 6 system clock duty steps.
   3. For up-down count mode, with high-resolution period: A loss of 12 system clock duty cycle steps.
4. If HRPWM period control is desired, only up-count or up-down count mode may be used. Down-count mode is not supported.
5. When phase shift between PWMs is the controlled parameter, having PWMs configured in asymmetric mode is typically easier to handle than symmetric mode. This is because when phase shift is greater 180 deg, it necessitates the synchronized PWM to be configured to count in the other direction on a sync event than how it was configured for phase shift < 180 deg. This must be handled by software.
6. If a constant 50 % duty cycle is desired, it is easier to use up-down count mode and have action qualifier events configured at CTR = 0 and PRD. If high-resolution period control is desired, this action qualifier configuration is not recommended.

This says up count mode is supported but down count mode is not. Did something change from this point, maybe a bug in software that hasnt yet been repaired?

Best,

Joel

Hi Marlyn,

I think I may have found the issues, but I cannot yet get to lab to test my board, let me know what you think?

For converter 1 - I am only setting the CMPA value for the high resolution register. I thought the CMPB value was automatically calculated from the CMPA value, the rising and falling edge delays in the dead-band module. Is this incorrect? Do I need to update CMPB every period in the same way I update CMPA, or does dead-band module automatically do this for me?

For converter 2 - I am setting both CMPA and CMPB values, this is a half-bridge converter. However, I set both duty cycles to (RES_PERIOD/2)-1. My dead-bands RED and FED are set to a non-zero value, therefore if I add up the two CMPA and CMPB values and then add on the FED and RED values, I believe I am exceeding the allowed time within the period and therefore this may lead to overlap of the signals... however, I got this code from a TI example so I am confused why it would ever be programmed in such a way unless the dead-band module is not used. Still cutting it close leaving only 1 cycle between signals, could lead to overlap. 

I'll have time to test these Monday. But with this in mind, maybe you can look through the code again and see if these look like they may be the issues?

Best,

JH

Hi Joel,

Joel Holland said:

However, I still have the same issue of overlap in my fourth PWM module, EPWM4, which does not use HRPWM mode. I *think* I have this set up for AHC, so not sure why I am seeing the overlap.

Looking at your dead band configuration for EPWM4 I don't see any issues. Are you changing the value for CMPA? I see the comment says initial value but if you are changing this value throughout your program this could be affecting the output. Can you also try disabling the TZ submodule configuration for now (it will make debugging easier if you can do this). Since the trip zone submodule comes after the deadband I just want to make sure that your dead band submodule is working correctly before the outputs make it to the trip zone submodule.

Joel Holland said:

This says up count mode is supported but down count mode is not. Did something change from this point, maybe a bug in software that hasnt yet been repaired?

If this was three years ago then we may not have known this was an issue at the time. Please take a look at the following from 7 months ago: https://e2e.ti.com/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/985066/tms320f28377d-high-resolution-pwm-and-dead-band 

Joel Holland said:

For converter 1 - I am only setting the CMPA value for the high resolution register. I thought the CMPB value was automatically calculated from the CMPA value, the rising and falling edge delays in the dead-band module. Is this incorrect? Do I need to update CMPB every period in the same way I update CMPA, or does dead-band module automatically do this for me?

CMPAHR only affects the A channel and is applied between the Chopper and Trip Zone submodules.  CMPBHR only affects the B channel is applied in the same place.  What's important here is that those delays are applied to the channels after the deadband module.  So CMPBHR is still acting on the EPWMxB signal even though it is truly just the inverted A signal from the deadband.  So yes,  each time you write to CMPAHR you should also write to CMPBHR.  

Joel Holland said:

therefore if I add up the two CMPA and CMPB values and then add on the FED and RED values, I believe I am exceeding the allowed time within the period and therefore this may lead to overlap of the signals... however, I got this code from a TI example so I am confused why it would ever be programmed in such a way unless the dead-band module is not used. Still cutting it close leaving only 1 cycle between signals, could lead to overlap. 

Would it be possible to draw this out? I am a bit confused on when you say "add up the two CMPA and CMPB values then add on the FED and RED values". This also goes back to my question on if you are changing the CMPA and CMPB values throughout your program or not. In the mode that you have selected, EPWMxA output from the deadband has RED applied and EPWMxB output from the deadband has FED applied. Which TI example were you referencing?

Best Regards,

Marlyn

Hi Marlyn,

Yes, I am changing the values of CMPA every time that I run the CLA and compute a new frequency/duty cycle for the converter. I was not however setting any values for CMPB because I had assumed in active high comp mode this would be handled automatically, maybe this is the source of my issues and I am working on the code now.

What I mean regarding the rising and falling edge delays is that we set the PRD value to a certain value, say 500. 
If we set CMPA and CMPB to PRD/2, i.e. 250 for 50% duty cycles, this leaves no "space" within the period to insert rising edge and falling edge delays. If we wanted "25" FED and RED between the high and low transitions of the PWMA and PWMB signals, this would add an extra 50 to the PRD, such that the total time taken for PWMA and PWMB to be ON with inserted delays would be 550 and therefore cause overlap because PWMA may go high again while there is still a falling edge on the PWMB output. Hopefully this makes sense. If not, I can draw out next time I reply what I mean. I can't remember the exact example I use, but I often see in the powerSUITE examples that duty cycles are set to half the period with no accounting for the lengths of the FED and RED. I had again assumed this must be taken care of in the dead-band module, but I must be wrong. Here is what I would suggest:

Set CMPA from the controller CLA program, say this is 200. 
Total period available = 500. 
Set CMPB to (500) - (CMPA) - (FED) - (RED)

This would still be active high complimentary but would allow the complimentary output to not overlap the other because it takes into account delays from the dead-band module. I think I am probably overcomplicating it though, since again I have never really seen anything like this in the example codes.

Best regards,
Joel

Heres an example from powerSUITE, TIDM1001, 2 phase LLC

void UpdateRegs(void)
{

ScaledPrd = (ScaledPrd < MIN_PERIOD)? MIN_PERIOD:ScaledPrd; //Clamp max freq
// ScaledPrd = (ScaledPrd > MAX_PERIOD)? MAX_PERIOD:ScaledPrd; //Clamp min freq - Already done by 'ScaledPrd = var1.Out*Max_Period'

Duty1 = Duty + Duty_adj - Duty_Shed_adj1; // Duty_adj = _IQ24(0.05)
Duty2 = Duty - Duty_adj - Duty_Shed_adj2;

Duty1 = (Duty1 < MIN_DUTY)? MIN_DUTY:Duty1; //Clamp max freq
Duty1 = (Duty1 > MAX_DUTY)? MAX_DUTY:Duty1; //Clamp min freq

Duty2 = (Duty2 < MIN_DUTY)? MIN_DUTY:Duty2; //Clamp max freq
Duty2 = (Duty2 > MAX_DUTY)? MAX_DUTY:Duty2; //Clamp min freq

CMPval1 = Duty1*(float)ScaledPrd;

CMPval2 = Duty2*(float)ScaledPrd;

(*ePWM[PWM_HS_PH1]).TBPRD = ScaledPrd;
(*ePWM[PWM_SRA_PH1]).TBPRD = ScaledPrd;
(*ePWM[PWM_HS_PH2]).TBPRD = ScaledPrd;
(*ePWM[PWM_SRA_PH2]).TBPRD = ScaledPrd;

(*ePWM[PWM_HS_PH1]).DBRED=RED;
(*ePWM[PWM_HS_PH1]).DBFED=FED;
(*ePWM[PWM_HS_PH2]).DBRED=RED;
(*ePWM[PWM_HS_PH2]).DBFED=FED;

(*ePWM[PWM_HS_PH1]).CMPB.bit.CMPB = CMPval1;
(*ePWM[PWM_HS_PH1]).CMPA.bit.CMPA = ScaledPrd - CMPval1; .....

There is no concern here about RED or FED in the total period, it looks like the CMPA and CMPB values are set without caring about the FED/RED values. So in a period in this example I would expect to see overlap, no? 

Hi Joel,

Joel Holland said:

If we set CMPA and CMPB to PRD/2, i.e. 250 for 50% duty cycles, this leaves no "space" within the period to insert rising edge and falling edge delays. If we wanted "25" FED and RED between the high and low transitions of the PWMA and PWMB signals, this would add an extra 50 to the PRD, such that the total time taken for PWMA and PWMB to be ON with inserted delays would be 550 and therefore cause overlap because PWMA may go high again while there is still a falling edge on the PWMB output. Hopefully this makes sense. If not, I can draw out next time I reply what I mean.

You've configured the deadband module as seen by the highlighed path below. EPWM output A from the AQ submodule is connected to the RED and FED paths. However note that only the Output A has RED and only the Output B has FED. To the right of that image, this is shown graphically, EPWMxA has a rising edge applied and EPWMxB has a falling edge applied (they do not overlap, even if the same RED/FED value is applied). 

Rising and Falling edge delays will take effect even after a zero or period event as long as there is an edge. In your current up-count scheme, you've configured your output to go "high" at a zero event and low on a CMPA match. Therefore, after the deadband submodule EPWMxA output will go low on a CMPA match and go high when TBCTR = 25 (0 + RED= 25). EPWMxB will have a falling edge delay applied so instead of going low on a CMPA match it will go low at (CMPA + FED = 250 + 25 = 275) and then go high when TBCTR = 0. After the delay is applied EPWMxB will be inverted. 

The same concept applies when you do up-down count mode as well. Let me know if the above was not clear and I can help explain further.

Would it be possible for you to remove the trip-zone configuration (just for debug) and see what your EPWM 4 outputs look like? 

Best Regards,

Marlyn

Hi, looking better, I understand the dead band module now. Here are the new screenshots: First is the EPWM4 running at 200KHz and second is the EPWM1 running at 1MHz. I updated the code to update both CMPA and CMPB for EPWM1 

// Divide period by 2 for up-down count mode
EPwm1Regs.CMPA.all = (uint32_t)((flyback_command*(float32_t)FLY_PERIOD_CLA/2) * (float32_t)((uint32_t)1 << 16) + 0.5f);
EPwm1Regs.CMPB.bit.CMPB = (FLY_PERIOD_CLA/2 - EPwm1Regs.CMPA.bit.CMPA);

// Update dead-times for the fly-back module
EPwm1Regs.DBFED.bit.DBFED = (FLY_PERIOD_CLA * 0.01);
EPwm1Regs.DBRED.bit.DBRED = (FLY_PERIOD_CLA * 0.01);

As it turned out I was not also updating CMPB but only CMPA. For the EPWM4 I didn't change much, I commented out the tripzone for both modules. 

EPwm4Regs.CMPA.bit.CMPA = (RES_PERIOD/4); // Maximum 50% duty cycle up-down count mode
EPwm4Regs.CMPB.bit.CMPB = (EPwm4Regs.TBPRD - EPwm4Regs.CMPA.bit.CMPA);      // Calculate CMPB from CMPA and max TBPRD

Looks better. There is clearly a deadband inserted, I believe on the yellow output. But there is no deadband on the blue output. This looks to be the exact same case for both PWM1 and PWM4 which seem to only have one dead-band inserted on the signals.

Any more suggestions?

Best regards and thanks again,
Joel

Hi Joel,

While I look at this just want to confirm that EPWMxA is the yellow output on your scope captures and the blue signal is EPWMxB?

Best Regards,

Marlyn

Hi, 

Sorry, should have mentioned, yes: PWMA is yellow and B is blue for PWM4. I just realised, that it is the other way round for PWM1, where blue is PWMA and yellow is PWMB. Apologies for this, didn't realise until I just tested again!

Thanks,
Joel

Hi Joel,

No worries, thank you for providing further clarification. I wanted to test the values you have but I don't know what FLY_PERIOD_CLA value is so the code below does not tell me what value you are setting for DBRED and DBFED. What is the time you want as a delay? If FLY_PERIOD_CLA is constantly changing I would recommend you set DBFED and DBRED to a fixed value just to see if you can see the correct applied value at the output. 

EPwm1Regs.DBFED.bit.DBFED = (FLY_PERIOD_CLA * 0.01);
EPwm1Regs.DBRED.bit.DBRED = (FLY_PERIOD_CLA * 0.01);

Additionally since you updated the count mode from up count to up and down count mode did you modify the action qualifier settings, can I please see the updated ones? 

Best Regards,

Marlyn

Hi Marlyn,

Thanks for your reply. The FLY_PERIOD_CLA is 100, this gives 1MHz freq. for a 100MHz PWM Clock on my oscilloscope. I defined it in CLA because this is where I update the registers. The DBRED and DBFED values are constant in the fly-back but are updated in the resonant converter as it is variable frequency. The resonant converter is PWM4A/B and the fly-back is PWM1A/B. Here are the action qualifiers:

EPwm1Regs.CMPCTL.bit.LOADAMODE = 1; // For asymmetric PWM generation and up-down count mode, load CMPA/CMPB on period match
EPwm1Regs.CMPCTL.bit.LOADBMODE = 1; // But the HRPWM configuration notes say to use LOADA/BMODE 2...
EPwm1Regs.CMPCTL.bit.SHDWAMODE = 0;
EPwm1Regs.CMPCTL.bit.SHDWBMODE = 0; // All writes via the CPU access the shadow register for both A and B outputs

// Set actions in the action qualifier module for PWMA
EPwm1Regs.AQCTLA.bit.CAU = 0x1; // Force PWMA low on count up
EPwm1Regs.AQCTLA.bit.ZRO = 0x2; // When TBCTR = ZRO, force PWMA high

// Set actions in the action qualifier module for PWMB
EPwm1Regs.AQCTLB.bit.CAU = 0x2; // Force PWMB high on CMPA match on count up
EPwm1Regs.AQCTLB.bit.ZRO = 0x1; // Force PWMB low on TBCTR = ZRO match

EPwm1Regs.DBCTL.bit.OUT_MODE = 3; // Fully enable dead-band for both falling and rising-edges
EPwm1Regs.DBCTL.bit.POLSEL = 2; // Active High Complimentary (AHC) Mode
//EPwm1Regs.DBFEDHR.bit.DBFEDHR = FLY_DEADTIME; // Set dead-time for falling edge
//EPwm1Regs.DBREDHR.bit.DBREDHR = FLY_DEADTIME; // Set dead-time for rising edge /* BEEN CHANGED BY JM HOLLAND */ TO HR BITS
EPwm1Regs.DBFED.bit.DBFED = FLY_DEADTIME;
EPwm1Regs.DBRED.bit.DBRED = FLY_DEADTIME;

and:

// CMPA/B Control
EPwm4Regs.CMPCTL.bit.LOADAMODE = 0;
EPwm4Regs.CMPCTL.bit.LOADBMODE = 0;
EPwm4Regs.CMPCTL.bit.SHDWAMODE = 0;
EPwm4Regs.CMPCTL.bit.SHDWBMODE = 0;

// If updating rising and falling edge delays, variable freq
EPwm4Regs.DBCTL.bit.SHDWDBREDMODE = 1; // Enable shadow load for RED
EPwm4Regs.DBCTL.bit.LOADREDMODE = 0; // Load on CTR = 0
EPwm4Regs.DBCTL.bit.SHDWDBFEDMODE = 1; // Enable shadow load for FED
EPwm4Regs.DBCTL.bit.LOADFEDMODE = 0; // Load on CTR = 0

// Set TBCLK = EPWMCLK = 100MHz
EPwm4Regs.TBCTL.bit.HSPCLKDIV = 0; // Clock ratio to SYSCLKOUT
EPwm4Regs.TBCTL.bit.CLKDIV = 0;
EPwm4Regs.TBCTL.bit.SYNCOSEL = 0x0; // Disable synchronised output

// Set initial modulation
EPwm4Regs.CMPA.bit.CMPA = EPwm4Regs.TBPRD-1; // Set initial compare A value, 50% duty cycle
EPwm4Regs.CMPB.bit.CMPB = EPwm4Regs.TBPRD-1; // Set initial compare B value, 50% duty cycle

// Set actions in action qualifier block (AQ)
EPwm4Regs.AQCTLA.bit.CAD = 0x2; // When TBCTR = CMPA on down count, force PWMA high
EPwm4Regs.AQCTLA.bit.CAU = 0x1; // When TBCTR = CMPA on up count, force PWMA low
EPwm4Regs.AQCTLB.bit.CBD = 0x1; // When TBCTR = CMPB on down count, force PWMB low
EPwm4Regs.AQCTLB.bit.CBU = 0x2; // When TBCTR = CMPB on up count, force PWMB high

// EPwm4Regs.DBCTL.bit.OUT_MODE = 0x00; // Fully disable dead-band module
EPwm4Regs.DBCTL.bit.OUT_MODE = 0x02; // Full enable for the dead-band module
EPwm4Regs.DBCTL.bit.POLSEL = 2; // Active high complementary (AHC)
EPwm4Regs.DBFED.bit.DBFED = RES_PERIOD_MIN*0.05; // Set initial dead-time for resonant module
EPwm4Regs.DBRED.bit.DBRED = RES_PERIOD_MIN*0.05; // Set initial dead-time for resonant module

Hope this helps.

Best regards,

Joel

Hi Joel,

I'd like to focus on EPWMx4 first and get that working with you. EPWM4 is running at 200KHz, based on your clock dividers I would say that TBPRD = 250, can you confirm this is true please?

Then I saw you had the following code:

EPwm4Regs.CMPA.bit.CMPA = (RES_PERIOD/4); // Maximum 50% duty cycle up-down count mode
EPwm4Regs.CMPB.bit.CMPB = (EPwm4Regs.TBPRD - EPwm4Regs.CMPA.bit.CMPA);      // Calculate CMPB from CMPA and max TBPRD

So in this case, I am making the assumption that RES_PERIOD is 250? Dividing that by 4 makes CMPA 62.5 (62) . CMPB would then be 187.5 (187).

In the new code you posted, the initial CMPA/CMPB values are 249 (which does not give a 50% duty cycle, like the comments state)

// Set initial modulation
EPwm4Regs.CMPA.bit.CMPA = EPwm4Regs.TBPRD-1; // Set initial compare A value, 50% duty cycle
EPwm4Regs.CMPB.bit.CMPB = EPwm4Regs.TBPRD-1; // Set initial compare B value, 50% duty cycle

Then the RED and FED delays are as below based on your latest reply. What is the value of RES_PERIOD_MIN?? 

EPwm4Regs.DBFED.bit.DBFED = RES_PERIOD_MIN*0.05; // Set initial dead-time for resonant module
EPwm4Regs.DBRED.bit.DBRED = RES_PERIOD_MIN*0.05; // Set initial dead-time for resonant module

It would be really helpful to understand the variables you have and when they are chaining/ what the range is constrained to. Its difficult to know if you are running into corner cases without this knowledge. 

You mentioned EPWM4 is a variable frequency application with changing RED/FED values. If it helps I would suggest keeping the values fixed (for debug) and see if you get the correct output (right after initialization). If the output is as you expect then we know the issue comes from later in the code when you update the period or RED/FED values.

Best Regards,

Marlyn

Hi Marlyn,

Thanks for the comments. I changed the CMPA/CMPB bits so that CMPA is (EPwm4Regs.TBPRD/2)-1 and CMPB is the TBPRD - CMPA, such that I get the 50% duty cycle. I still get the same issues. 

Because my controller does not have any input to the ADC, despite this being a variable frequency application, the output is currently fixed at the minimum output frequency, such that the FED and RED are also fixed at a portion of this frequency. RES_PERIOD_MIN is the highest frequency, 400kHz or 250. RES_PERIOD_MAX is 500, or 200kHz. The plan is eventually this will be 25-50% variable duty cycle with variable frequency which is why I have coded to have this particular up-down symmetrical count scheme.

For some reason, the controller seems to be inserting both delays on one output? There is a large dead-time between the falling edge of PWMB and rising edge of PWMA, but nothing at the next transition toggle.

The initial modulations are set to the same:

EPwm4Regs.CMPA.bit.CMPA = (EPwm4Regs.TBPRD/2)-1; 50% duty cycle
EPwm4Regs.CMPB.bit.CMPB = EPwm4Regs.TBPRD - EPwm4Regs.CMPA; 50% duty cycle

Best regards,

Joel

Looks as though problem is definitely in the dead-band configuration - I have just completely disabled it and changed the CMPA/CMPB limits manually in my code, and the waveforms look better:

I would still like to debug the dead-band module to not have to worry about any overlaps in my outputs to be guaranteed in code.

Best,
Joel

Hi Joel,

Previously in your code, you had the OUT_MODE bit as 3 which is what enables both RED and FED, but in the latest code you provided this value was changed to 2 which means only RED is applied. I think this is why you only see one delay in your output. I made some modifications to our deadband example within C2000Ware. With the configuration provided, the outputs have both RED and FED delay (of the right amount), with a 400kHz output.

Please compare your deadband configuration and compare values to the below. Note that you don't need to provide a CMPB value for EPWM4 since you aren't using High Resolution PWM. The input into the deadband module is only EPWMxA since you are configuring for Active High Complementary. 

Joel Holland said:

RES_PERIOD_MIN is the highest frequency, 400kHz or 250. RES_PERIOD_MAX is 500, or 200kHz.

The calculations to find the TBPRD are dependent on your count mode. Since you are using up and down count mode, a 400kHz output is actually a TBPRD value of 125 not 250. You'll also need to recalculate the TBPRD for RES_PERIOD_MAX. Below is an example of the calculation:

T_pwm = 1/F_pwm = (1/400kHz) = 2.5 usec

TBCLK = EPWMCLK/ (HSPCLKDIV * CLKDIV) = 100MHz/ (1*1) = 100 MHz

T_TBCLK = 1/TBCLK = 1/100MHz = 10 nsec

T_pwm = 2*TBPRD*T_TBCLK  -> TBPRD = T_pwm / (2*T_TBCLK) = (2.5 usec)/ (2 * 10 nsec) = 125

* Note: I used EPWM1 in the below but this is to help with EPWM4 setup

//
// Included Files
//
#include "F28x_Project.h"

//
// Defines
//
#define RES_PERIOD_MIN 125 //400kHz

//
// Globals
//
Uint32 EPwm1TimerIntCount;

//
// Function Prototypes
//
void InitEPwm1Example(void);
__interrupt void epwm1_isr(void);

//
// Main
//
void main(void)
{
//
// Step 1. Initialize System Control:
// PLL, WatchDog, enable Peripheral Clocks
// This example function is found in the F2837xD_SysCtrl.c file.
//
    InitSysCtrl();

//
// Step 2. Initialize GPIO:
// This example function is found in the F2837xD_Gpio.c file and
// illustrates how to set the GPIO to its default state.
//
//    InitGpio();

//
// enable PWM1, PWM2 and PWM3
//
    CpuSysRegs.PCLKCR2.bit.EPWM1=1;

//
// For this case just init GPIO pins for ePWM1, ePWM2, ePWM3
// These functions are in the F2837xD_EPwm.c file
//
    InitEPwm1Gpio();

//
// Step 3. Clear all interrupts and initialize PIE vector table:
// Disable CPU interrupts
//
    DINT;

//
// Initialize the PIE control registers to their default state.
// The default state is all PIE interrupts disabled and flags
// are cleared.
// This function is found in the F2837xD_PieCtrl.c file.
//
    InitPieCtrl();

//
// Disable CPU interrupts and clear all CPU interrupt flags:
//
    IER = 0x0000;
    IFR = 0x0000;

//
// Initialize the PIE vector table with pointers to the shell Interrupt
// Service Routines (ISR).
// This will populate the entire table, even if the interrupt
// is not used in this example.  This is useful for debug purposes.
// The shell ISR routines are found in F2837xD_DefaultIsr.c.
// This function is found in F2837xD_PieVect.c.
//
    InitPieVectTable();

//
// Interrupts that are used in this example are re-mapped to
// ISR functions found within this file.
//
    EALLOW; // This is needed to write to EALLOW protected registers
    PieVectTable.EPWM1_INT = &epwm1_isr;
    EDIS;   // This is needed to disable write to EALLOW protected registers

//
// Step 4. Initialize the Device Peripherals:
//
    EALLOW;
    CpuSysRegs.PCLKCR0.bit.TBCLKSYNC =0;
    EDIS;

    InitEPwm1Example();

    EALLOW;
    CpuSysRegs.PCLKCR0.bit.TBCLKSYNC =1;
    EDIS;

//
// Step 5. User specific code, enable interrupts:
// Initialize counters:
//
    EPwm1TimerIntCount = 0;

//
// Enable CPU INT3 which is connected to EPWM1-3 INT:
//
    IER |= M_INT3;

//
// Enable EPWM INTn in the PIE: Group 3 interrupt 1-3
//
    PieCtrlRegs.PIEIER3.bit.INTx1 = 1;

//
// Enable global Interrupts and higher priority real-time debug events:
//
    EINT;  // Enable Global interrupt INTM
    ERTM;  // Enable Global realtime interrupt DBGM

//
// Step 6. IDLE loop. Just sit and loop forever (optional):
//
    for(;;)
    {
        asm ("          NOP");
    }
}

//
// epwm1_isr - EPWM1 ISR
//
__interrupt void epwm1_isr(void)
{
    EPwm1TimerIntCount++;

    //
    // Clear INT flag for this timer
    //
    EPwm1Regs.ETCLR.bit.INT = 1;

    //
    // Acknowledge this interrupt to receive more interrupts from group 3
    //
    PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;
}

//
// InitEPwm1Example - Initialize EPWM1 configuration
//
void InitEPwm1Example()
{
    EPwm1Regs.TBPRD = RES_PERIOD_MIN;             // Set timer period
    EPwm1Regs.TBPHS.bit.TBPHS = 0x0000;           // Phase is 0
    EPwm1Regs.TBCTR = 0x0000;                     // Clear counter

    //
    // Setup TBCLK
    //
    EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up and down
    EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE;        // Disable phase loading
    EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;       // Clock ratio to SYSCLKOUT
    EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1;

    EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;    // Load registers every ZERO
    EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
    EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
    EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;

    //
    // Setup compare
    //
    EPwm1Regs.CMPA.bit.CMPA = RES_PERIOD_MIN/2; // 50% Duty

    //
    // Set actions
    //
    EPwm1Regs.AQCTLA.bit.CAU = AQ_CLEAR;
    EPwm1Regs.AQCTLA.bit.CAD = AQ_SET;

    //
    // Active High Complementary - Setup Deadband
    //

      EPwm1Regs.DBCTL.bit.IN_MODE = DBA_ALL;          // 0 (default)

      EPwm1Regs.DBCTL.bit.DEDB_MODE = 0;              // 0 (default)

      EPwm1Regs.DBRED.bit.DBRED = RES_PERIOD_MIN*0.05;
      EPwm1Regs.DBFED.bit.DBFED = RES_PERIOD_MIN*0.05;

      EPwm1Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;       // 2

      EPwm1Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;  // 3

      EPwm1Regs.DBCTL.bit.OUTSWAP = 0;                // 0 (default)

    //
    // Interrupt where we will change the Deadband
    //
    EPwm1Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO;    // Select INT on Zero event
    EPwm1Regs.ETSEL.bit.INTEN = 1;               // Enable INT
    EPwm1Regs.ETPS.bit.INTPRD = ET_1ST;          // Generate INT on 1st event
}

//
// End of file
//

Best Regards,

Marlyn

"Note that you don't need to provide a CMPB value for EPWM4 since you aren't using High Resolution PWM. The input into the deadband module is only EPWMxA since you are configuring for Active High Complementary."

Hi Marlyn, thank you very much for the code idea above. I will implement it and get back to you. In meanwhile,
Your comment above - so how should my code change for EPWM1 where I am indeed using HRPWM mode? I need to provide both a CMPA and a CMPB value for those ones, unlike if I was not using HRPWM? Why is this the case? I would expect that active high complimentary and the dead band module are still available in HRPWM mode? 

In HRPWM mode is it thus better to provide CMPA and CMPB and by-pass the dead band module and ensure myself in code that they never overlap?

Hi Joel,

Joel Holland said:

so how should my code change for EPWM1 where I am indeed using HRPWM mode? I need to provide both a CMPA and a CMPB value for those ones, unlike if I was not using HRPWM? Why is this the case?

For EPWM1, yes you would need to write to CMPBHR as well as CMPAHR. This goes back to a previous reply: "CMPAHR only affects the A channel and is applied between the Chopper and Trip Zone submodules.  CMPBHR only affects the B channel is applied in the same place.  What's important here is that those delays are applied to the channels after the deadband module.  So CMPBHR is still acting on the EPWMxB signal even though it is truly just the inverted A signal from the deadband.  So yes, each time you write to CMPAHR you should also write to CMPBHR." The high resolution part is being applied after the deadband so you still need to provide both for HRPWM. 

Also note that for HRPWM, since you are using the deadband you have to also set half clocking. The formula for your rising and falling edge delay values will change. This is the note in the TRM: "High-resolution dead-band RED and FED requires Half-Cycle clocking mode (DBCTL[HALFCYCLE] = 1)."

Joel Holland said:

I would expect that active high complimentary and the dead band module are still available in HRPWM mode? 

Yes, you can still use the active high complimentary mode of the deadband module even while in HRPWM mode. I wouldn't by-pass the deadband module if you are using the up-down count mode. 

Best Regards,

Marlyn

Hello Marlyn,

Do I understand then, that CMPA and CMPB are written as normal, with deadband set as normal - so we write to CMPA, CMPB, RED, FED. To use the dead-band, we then also have to write to CMPAHR, CMPBHR, DBREDHR, DBFEDHR, following on from this module, which applies the high resolution to the pre-existing CMPA and CMPB values?

Best regards,

Joel

Hi Joel,

Yes, your understanding is correct. HRPWM enhancements happen throughout multiple submodules,

Best Regards,

Marlyn