TMS320F280049: EPWMCLK Definition

Trey German8

Expert 1950 points

C2000 Team,

I'm messing around with the EPWM and maybe I'm just not looking in the right place, but I'm finding the documentation on the EPWMCLK to be a little lacking. I've found a forum answer from Vivek S that appears to indicate the clock divider has been undocumented. However, I'm seeing mentions of a user configurable divider in the driverlib:

//*****************************************************************************
//
//! Set the time base clock and the high speed time base clock count pre-scaler
//!
//! \param base is the base address of the EPWM module.
//! \param prescaler is the time base count pre scale value.
//! \param highSpeedPrescaler is the high speed time base count pre scale
//!        value.
//!
//! This function sets the pre scaler(divider)value for the time base clock
//! counter and the high speed time base clock counter.
//! Valid values for pre-scaler and highSpeedPrescaler are EPWM_CLOCK_DIVIDER_X,
//! where X is 1,2,4,8,16, 32,64 or 128.
//! The actual numerical values for these macros represent values 0,1...7.
//! The equation for the output clock is:
//!   TBCLK = EPWMCLK/(highSpeedPrescaler * pre-scaler)
//!
//! \b Note: EPWMCLK is a scaled version of SYSCLK. At reset EPWMCLK is half
//!          SYSCLK.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_setClockPrescaler(uint32_t base, EPWM_ClockDivider prescaler,
                       EPWM_HSClockDivider highSpeedPrescaler)

Based on the above two sources of information, this would lead me to believe that EPWMCLK is always SYSCLK/2. Is that correct? If so, it sure would be nice if that was documented in the DS or TRM. I've searched through both documents for EPWMCLK and no where is this "fixed" divider called out.

Also further down in the HRPWM sections there are some tables that include information that is only valid for EPWMCLK of 100MHz. Assuming my hypothesis that EPWMCLK is always SYSCLK/2 is correct, these tables should be updated to reflect the maximum EPWMCLK frequency of 50MHz for this device.

Best,

Trey

over 4 years ago

0 Trey German8 over 4 years ago

Expert 1950 points

Also while I'm here, I think there's an error in the Sync In config API in driverlib:

//*****************************************************************************
//
//! The following values define the \e syncSrc parameter for
//! SysCtl_setSyncInputConfig(). Note that some of these are only valid for
//! certain values of \e syncInput. See device technical reference manual for
//! info on time-base counter synchronization for details.
//
//*****************************************************************************
typedef enum
{
    //! EPWM1SYNCOUT
    SYSCTL_SYNC_IN_SRC_EPWM1SYNCOUT     = 0,
    //! EPWM4SYNCOUT
    SYSCTL_SYNC_IN_SRC_EPWM4SYNCOUT     = 1,
    //! EPWM7SYNCOUT
    SYSCTL_SYNC_IN_SRC_EPWM7SYNCOUT     = 2,
    //! ECAP1SYNCOUT
    SYSCTL_SYNC_IN_SRC_ECAP1SYNCOUT     = 4,
    //! EXTSYNCIN1--Valid for all values of syncInput
    SYSCTL_SYNC_IN_SRC_EXTSYNCIN1       = 5,
    //! EXTSYNCIN2--Valid for all values of syncInput
    SYSCTL_SYNC_IN_SRC_EXTSYNCIN2       = 6,
} SysCtl_SyncInputSource;

Header file says Ext Sync 2 is valid for all choices of sync input. However TRM shows that only EXTSYNCIN1 is valid for EPWM1SYNCIN.

Best,

The T Machine

0 Subrahmanya over 4 years ago in reply to Trey German8

TI__Mastermind 24095 points

Hi,

You are correct.
Please refer to the "Figure 18-7. Time-Base Counter Synchronization Scheme"

Trey German8 said:
Header file says Ext Sync 2 is valid for all choices of sync input. However TRM shows that only EXTSYNCIN1 is valid for EPWM1SYNCIN.

only EXTSYNCIN1 is valid for EPWM1SYNCIN. So, EXTSYNCIN2 is available for other EPWM*SYNCIN.

0 Trey German8 over 4 years ago in reply to Subrahmanya

Expert 1950 points

Awesome, thanks for confirming.

Can you confirm that EPWMCLK is always SYSCLK/2?

+1 Vivek Singh over 4 years ago in reply to Trey German8

TI__Guru** 116581 points

Trey,

On this device, EPWMCLK is SYSCLK (there is no divider). The comment in driverlib function is carry forward from other device where SYSCLK was 200MHz. We'll get this corrected. Thank you for the feedback.

Regards,

Vivek Singh

0 Trey German8 over 4 years ago in reply to Vivek Singh

Expert 1950 points

Thanks Vivek! Please make sure EPWMCLK is defined in the TRM as well as removing the comment in the driverlib function.

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TMS320F280049: EPWMCLK Definition