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Original question:

Confuse Library setting versa F28M36 Datasheet description

F28M35H52C: Ethernet pinout

Christian L
Intellectual 630 points

Part Number: F28M35H52C

The latest support files for the concerto chip (v220) are missing some defines in the gpio.h. In particular, it is missing defines relevant when running M3 primary mode 3 pinouts. This is mentioned in the following rather old post Confuse Library setting versa F28M36 Datasheet description - C2000 microcontrollers forum - C2000Tm︎ microcontrollers - TI E2E support forums

We have a new PCB design where we have to use M3-Primary-Mode3 for ethernet but are unable to make it work. Could someone from TI please help us, by double-checking the above post/solution, and also inspecting the below code, which we now use for the pinout in mode 3:

#define GPIO_PG6_MIITXCK 0x00061803
#define GPIO_PF6_MIIRXD2 0x00051803
void ethernetPinSetup()
{
// Ethernet pin setup
GPIODirModeSet( GPIO_PORTA_BASE, GPIO_PIN_7 | GPIO_PIN_6 | GPIO_PIN_5 | GPIO_PIN_4 | GPIO_PIN_3 | GPIO_PIN_2, GPIO_DIR_MODE_HW);
GPIOPadConfigSet( GPIO_PORTA_BASE, GPIO_PIN_7 | GPIO_PIN_6 | GPIO_PIN_5 | GPIO_PIN_4 | GPIO_PIN_3 | GPIO_PIN_2, GPIO_PIN_TYPE_STD);
GPIOPinConfigure( GPIO_PA2_MIITXD2 ); // PA2_GPIO2
GPIOPinConfigure( GPIO_PA3_MIITXD1 ); // PA4_GPIO3
GPIOPinConfigure( GPIO_PA4_MIITXD0 ); // PA4_GPIO4
GPIOPinConfigure( GPIO_PA5_MIIRXDV ); // PA5_GPIO5
GPIOPinConfigure( GPIO_PA6_MIIRXCK ); // PA6_GPIO6
GPIOPinConfigure( GPIO_PA7_MIIRXER ); // PA7_GPIO7

GPIODirModeSet( GPIO_PORTB_BASE, GPIO_PIN_7, GPIO_DIR_MODE_HW );
GPIOPadConfigSet( GPIO_PORTB_BASE, GPIO_PIN_7, GPIO_PIN_TYPE_STD );
GPIOPinConfigure( GPIO_PB7_MIIRXD1 ); // PB7_GPIO15

GPIODirModeSet( GPIO_PORTE_BASE, GPIO_PIN_4, GPIO_DIR_MODE_HW );
GPIOPadConfigSet( GPIO_PORTE_BASE, GPIO_PIN_4, GPIO_PIN_TYPE_STD );
GPIOPinConfigure( GPIO_PE4_MIIRXD0 ); // PE4_GPIO28

GPIODirModeSet( GPIO_PORTF_BASE, GPIO_PIN_6 | GPIO_PIN_5 | GPIO_PIN_4 | GPIO_PIN_3 | GPIO_PIN_2, GPIO_DIR_MODE_HW );
GPIOPadConfigSet( GPIO_PORTF_BASE, GPIO_PIN_6 | GPIO_PIN_5 | GPIO_PIN_4 | GPIO_PIN_3 | GPIO_PIN_2, GPIO_PIN_TYPE_STD );
GPIOPinConfigure( GPIO_PF2_MIIPHYINTRn ); // PF2_GPIO34
GPIOPinConfigure( GPIO_PF3_MIIMDC ); // PF3_GPIO35
GPIOPinConfigure( GPIO_PF4_MIIMDIO ); // PF4_GPIO36
GPIOPinConfigure( GPIO_PF5_MIIRXD3 ); // PF5_GPIO37
GPIOPinConfigure( GPIO_PF6_MIIRXD2 ); // PF6_GPIO38

GPIODirModeSet( GPIO_PORTG_BASE, GPIO_PIN_7 | GPIO_PIN_6 | GPIO_PIN_5 | GPIO_PIN_3 | GPIO_PIN_2, GPIO_DIR_MODE_HW);
GPIOPadConfigSet( GPIO_PORTG_BASE, GPIO_PIN_7 | GPIO_PIN_6 | GPIO_PIN_5 | GPIO_PIN_3 | GPIO_PIN_2, GPIO_PIN_TYPE_STD);
GPIOPinConfigure( GPIO_PG2_MIICOL); // PG2_GPIO42
GPIOPinConfigure( GPIO_PG3_MIICRS); // PG3_GPIO43
GPIOPinConfigure( GPIO_PG5_MIITXEN); // PG5_GPIO45
GPIOPinConfigure( GPIO_PG6_MIITXCK); // PG6_GPIO46
GPIOPinConfigure( GPIO_PG7_MIITXER); // PG7_GPIO47

GPIODirModeSet( GPIO_PORTH_BASE, GPIO_PIN_0, GPIO_DIR_MODE_HW);
GPIOPadConfigSet( GPIO_PORTH_BASE, GPIO_PIN_0, GPIO_PIN_TYPE_STD);
GPIOPinConfigure( GPIO_PH0_MIIPHYRSTn); // PH0_GPIO48

GPIODirModeSet( GPIO_PORTC_BASE, GPIO_PIN_4, GPIO_DIR_MODE_HW );
GPIOPadConfigSet( GPIO_PORTC_BASE, GPIO_PIN_4, GPIO_PIN_TYPE_STD );
GPIOPinConfigure( GPIO_PC4_MIITXD3 ); // PC4_GPIO68
}

  • 0
    Intellectual 630 points

    Hi again TI,

    Is someone looking into this issue?

    I guess you could easily verify the missing defines in the support code as a start, that is, whether the following is correct:

    #define GPIO_PG6_MIITXCK 0x00061803
    #define GPIO_PF6_MIIRXD2 0x00051803

  • 0 in reply to Christian L
    Intellectual 630 points

    Hi again TI,

    Is someone looking into this issue?

    I guess you could easily verify the missing defines in the support code as a start, that is, whether the following is correct:

    #define GPIO_PG6_MIITXCK 0x00061803
    #define GPIO_PF6_MIIRXD2 0x00051803

  • 0 in reply to Christian L
    Intellectual 630 points

    Hi again TI,

    Can I at least get a reply/comment on this?

  • 0 in reply to Christian L
    Intellectual 630 points

    Hi again, 

    I must say I am really disappointed to see no responses on this. E2E has worked ok to resolve the few issues I have had over the last ten years. But it seems I can no longer get a response, even when it concerns missing code in the TI support files.

    Christian 

  • 0 in reply to Christian L
    TI__Genius 16881 points

    Hi Christian, I am terribly sorry that you have not received a reply.  This is unacceptable and we are working to assign this thread to a subject matter expert that will reply today.  Please accept my sincere apologies.

    Joe

  • 0
    TI__Guru 54445 points

    Hi Christian,

    I have reviewed your code and haven't spotted any issues. I was able to find the #defines you mentioned in v220, so it appears they were added at some point--although the MIITXCK define is GPIO_PG6_MIITXCLK with an extra L. The values do match the values in the #defines you've used above.

    Have you tried examining the configurations of these pins in the GPIO registers in the CCS registers view? It would be good to confirm the actual register values match the mux values in the data sheet and just to confirm that no other code has inadvertently overwritten any of these configurations at some point.

    Whitney

  • 0 in reply to Whitney Dewey
    TI__Mastermind 42195 points

    Christian,

     In addition to Whitney's suggestions do you mind sharing the C2000-> PHY schematic connections? There may be a HW issue preventing communication. I can't guarantee that we will find something, but I will review.

    I am unfamiliar with "mode 3 pinouts", can you describe what you mean?

    Regards,
    Cody 

  • 0 in reply to Cody Watkins
    Intellectual 630 points

    Hi Cody and Whitney,

    Thanks for your help and suggestions.

    We are going over everything again. While redoing the new pinout using your "C2000 Pin Mux Utility" we noticed having to select the peripherals in a particular order, to avoid pin collisions. Please check if our selection is indeed valid and possible. I attach screenshots from the  "C2000 Pin Mux Utility" below.

    Many thanks,

    Christian

  • 0 in reply to Christian L
    TI__Guru 54445 points

    Hi Christian,

    I didn't spot any issues in the screenshots you shared.

    Whitney

  • 0 in reply to Whitney Dewey
    Intellectual 630 points

    Thanks Whitney,

    We still wonder about the Pin Mux Utility though, since it seemingly can produce different values for the Registers fields (the right hand panel in the window) depending on the order one selects the peripherals. One way for you to help would be to check if both attached pinout files are valid. They both produce the same final pinout, and pin count, but the Register fields within the utility are different.

    When examining the configurations of pins in the GPIO registers in the CCS registers view, which of the two should I compare against?

     

    cpu_pinout.zip

    Christian 

  • 0 in reply to Christian L
    TI__Guru 54445 points

    It looks like the only differences between those pin mappings are in port D and port H. Judging by your ethernetPinSetup code above, there are no Ethernet pins configured in port D and the only one in port H is pin 0 and it looks properly configured in both. So at least where Ethernet is concerned, you can can use either one as a reference.

    Whitney