TMS320F28377S: TMS320F28377S pwm shadow mode configuration

coke kou

Part Number: TMS320F28377S

Dear TI engineers，

I have some doubt about AQSFRC.RLDCSF=0x11. The configuration is below.

The destination of this configuration seems to use shadow mode. But EPwm1Regs.AQSFRC.bit.RLDCSF = 3 make the shadow mode not work.

So，how to realize this configuration？

Looking forward for your direction.

	EPwm1Regs.TBCTL.bit.HSPCLKDIV = 0;
	EPwm1Regs.TBCTL.bit.CLKDIV = 0;					//TBCLK = EPWMCLK
	EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN;	// Symmetrical mode
	EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE;			// Master module,not load timebase from TBPHS
	EPwm1Regs.TBCTL.bit.PRDLD = TB_SHADOW;			// load TBPRD from its shadow ,when TBCTR is 0
	EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_CTR_ZERO;		//TBCTR = 0x0000, EPWMxSYNCO Synchronization Output
	EPwm1Regs.TBPRD = 6410;							// 200M / 6410.2 / 2 = 15.6KHz
	EPwm1Regs.TBPHS.bit.TBPHS = 0;						// Set Phase register to zero
	EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;		//CMPA Register Operating shadow Mode
	EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;		//CMPB Register Operating shadow Mode
	EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_PRD;	//CMPA load from shadow , on CTR=PRD
	EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_PRD; 	//CMPB load from shadow,  on CTR=PRD
	// duty = CMPA /TBPRD
	EPwm1Regs.AQCTLA.bit.CAU = AQ_SET;			//when the counter rising equals the active CMPA,force EPWMxA output low.
	EPwm1Regs.AQCTLA.bit.CAD = AQ_CLEAR;		//when the counter falling equals the active CMPA ,force EPWMxA output high.

	//EPwm1Regs.DBCTL.bit.MODE = DB_FULL_ENABLE;	// enable Dead-band module
	EPwm1Regs.DBCTL.bit.IN_MODE = DBA_ALL;			//EPWMxA In is the source for both falling-edge and rising-edge delay.
//	EPwm1Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;	//both rising and falling edge of EPWM1A have dead band.
	EPwm1Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;		// EPWMxB is inverter of EPWMxA
	
	EPwm1Regs.DBFED.all = 300;						// falling delay 2.5us
	EPwm1Regs.DBRED.all = 300;						// rising delay 2.5us

	EPwm1Regs.ETSEL.bit.INTSEL = 1;  				// EPWMx_INT interrupt active when TBCTR = 0x0000, under overflow ,INV interrupt
	EPwm1Regs.ETSEL.bit.INTEN = 1;   				// enable interrupt
	EPwm1Regs.ETPS.bit.INTPRD = 1;   				// Generate INT on first event 

	EPwm1Regs.TZSEL.bit.CBC1 = TZ_ENABLE;			// Enable TZ1 as a CBC trip source for this ePWM module,OVC
	EPwm1Regs.TZSEL.bit.OSHT2 = TZ_ENABLE;			// Enable TZ2 as a One-shot trip source for this ePWM module,BUSOV
	EPwm1Regs.TZCTL.bit.TZA = TZ_FORCE_LO;			// Force EPWMxA to a low state
	EPwm1Regs.TZCTL.bit.TZB = TZ_FORCE_LO;			// Force EPWMxB to a low state
	EPwm1Regs.AQSFRC.bit.RLDCSF = 3;

over 4 years ago

0 Aditya Dholakia over 4 years ago

TI__Expert 7150 points

Hi,

I couldn't clearly get what your requirement is. To clear things, the AQSFRC is used for the software forced events where the EPWM can be pulled high or low at the desired instance as configured in the AQSFRC and AQCSFRC registers.

Incase you are trying to run normal operation for EPWM then you would want to use the AQCTL registers for configuration of shadow mode.

Thanks,

Aditya

0 coke kou over 4 years ago in reply to Aditya Dholakia

Intellectual 300 points

Dear Aditya，

Thanks for your reply. The code is not written by myself. So, I do not know why should configure like these. In my mean，AQSFRC.RLDCSF=0x11 seems to disable the shadow mode. But，shadow mode maybe wanted in project.

So，how to realize AQSFRC.RLDCSF=0x11？

Looking forward for your direction.

0 Aditya Dholakia over 4 years ago in reply to coke kou

TI__Expert 7150 points

Hi Coke,

By shadow mode, I believe you want to use the shadow mode under normal PWM operation. For that purpose, you can configure the CMPCTL register bits.

The code that you've shared already has the configuration for shadow mode. You need not do anything extra.

	EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;		//CMPA Register Operating shadow Mode
	EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;		//CMPB Register Operating shadow Mode
	EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_PRD;	//CMPA load from shadow , on CTR=PRD
	EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_PRD; 	//CMPB load from shadow,  on CTR=PRD

Thanks,

Aditya

0 coke kou over 4 years ago in reply to Aditya Dholakia

Intellectual 300 points

Dear Aditya，

I know the configuration above is ok. But I do not know what influence would happen when AQSFRC.RLDCSF=0x11 not be banned.

Looking forward for your direction.

0 Aditya Dholakia over 4 years ago in reply to coke kou

TI__Expert 7150 points

The AQSFRC[RLDCSF] register configuration is for the software forced action shadow mode. When you enable the software force shadow load, you can setup the PWM to act in a particular way i.e. pull the PWM low, high or toggle on every software forced event using the register AQCSFRC bits. This is a higher priority condition over the normal operation and to be used for particular event operation.

Hope this helps.

Thanks,

Aditya

0 coke kou over 4 years ago in reply to Aditya Dholakia

Intellectual 300 points

Dear Aditya，

To make the question easily, what are the difference between 2 and 3 in bit RLDCSF? How do I realize ‘Load immediately’？

Looking forward for your direction.

0 Aditya Dholakia over 4 years ago in reply to coke kou

TI__Expert 7150 points

Please refer to this description from epwm.h file:

//*****************************************************************************
//
//! Sets up Action qualifier continuous software load mode.
//!
//! \param base is the base address of the EPWM module.
//! \param mode is the mode for shadow to active load mode.
//!
//! This function sets up the AQCFRSC register load mode for continuous
//! software force reload mode. The software force actions are determined by
//! the EPWM_setActionQualifierContSWForceAction() function.
//! Valid values for mode are:
//!   - EPWM_AQ_SW_SH_LOAD_ON_CNTR_ZERO        - shadow mode load when counter
//!                                               equals zero
//!   - EPWM_AQ_SW_SH_LOAD_ON_CNTR_PERIOD      - shadow mode load when counter
//!                                               equals period
//!   - EPWM_AQ_SW_SH_LOAD_ON_CNTR_ZERO_PERIOD - shadow mode load when counter
//!                                               equals zero or period
//!   - EPWM_AQ_SW_IMMEDIATE_LOAD               - immediate mode load only
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_setActionQualifierContSWForceShadowMode(uint32_t base,
                                             EPWM_ActionQualifierContForce mode)

The bit 3 is used to disable the shadow mode (as soon as the software force event happens, the action mentioned in the AQCSFRC takes place).

For bit 2, as soon as a software forced event happens, the action happens in shadow fashion where the EPWM is pulled high, low or toggled when CMP is ZERO or PRD and not immediately at any value of CMP.

There'll be certain delay when you set the bit config to 2 instead of 3.

0 coke kou over 4 years ago in reply to Aditya Dholakia

Intellectual 300 points

Dear Aditya，

Thanks for your reply.

The ‘event counter’ in datasheet means TBCTR？ Did it mean when software force event happens，it would not work until TBCTR equal zero or period？

Looking forward for your direction.

+1 Aditya Dholakia over 4 years ago in reply to coke kou

TI__Expert 7150 points

coke kou said:
The ‘event counter’ in datasheet means TBCTR？

Correct.

coke kou said:
Did it mean when software force event happens，it would not work until TBCTR equal zero or period？

That's correct. That's the idea of shadow mode.

Thanks,

Aditya

C2000™︎ microcontrollers

C2000 microcontrollers forum

TMS320F28377S: TMS320F28377S pwm shadow mode configuration