TMS320F280025: I2C SDL/SCL rising and falling time

Hitoshi Sugawara

Part Number: TMS320F280025

Hi Experts,

According to the datasheet www.ti.com/lit/sprsp45 at 7.14.2.1.1 I2C Timing Requirement "Fast mode", there is 300ns(max) for T5 to T8. They are Rise time for SDA and SCL and Fall time for SDA and SCL.
Could you please what causes the longer time 300ns(max)?
I think if T11 "Cb" load is close to 400pF, the rising and falling time would be longer.

Thank you for your kind check.
Best regards,
Hitoshi Sugawara

over 2 years ago

+1 Manoj Santha Mohan over 2 years ago

TI__Guru 55700 points

Hitoshi,

I2C timing requirement table comes from original I2C specs (UM10204) and not actually defined by TI. T5-T8 parameter just says that rise / fall time should be less than 300ns for you to be compliant with I2C specs.

T11 just specifies the maximum capacitive load on the I2C bus.

Regards,

Manoj

+1 Hitoshi Sugawara over 2 years ago in reply to Manoj Santha Mohan

TI__Mastermind 18650 points

Hi Manoj,
Thank you for your kind check. I understand that it is depending the customer's design. I believe that the pull up resister and capacitive load are the majority of the spec.
Best regards,
Hitoshi

C2000™︎ microcontrollers

C2000 microcontrollers forum

TMS320F280025: I2C SDL/SCL rising and falling time