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TMS320F28027: UART BREAK problem

Gerald
Genius 9570 points

Part Number: TMS320F28027

Hi Experts,

May I ask for help? Our customer is asking for assistance. He is using UART (SCI) of this microcontroller for communication and it has a strange failure.
It is configured so that it stays in the sleep mode until the address bit and correct address are received.
The problem is that in a case of 0x00 byte (start-bit, address bit=0, 7x data=0, EVEN parity - totally 10 zeros) , sometimes SCI generates BREAK event but ONLY in a sleep mode and never after WAKE.
Can you please tell us, do you have any information concerning this issue?

Maybe BREAK detection in some cases requires less amount of zeros?

I hope you can help us. Thank you so much in advance.

Kind regards,
Gerald

  • 0
    TI__Mastermind 26760 points

    Hi Gerald,

    Can you please provide the desired baud rate for the customer as well as what their measured baud rate is? Note that the break detect flag will occur after 9.625 low bit periods.

    Best Regards,

    Marlyn

  • 0 in reply to Marlyn Rosales Castaneda20
    TI__Genius 9570 points

    Hi Marlyn,

    Thanks for your response. Customer said: the master has exactly 57600 and the slave 56818 baud (the closest value we got, about 1% difference. Error is generated by the slave only when it is in SLEEP mode during data exchange with other slaves. As I see from the datasheet, BREAK time count starts after start-bit detection, so totally line must be in low-state during about 11x bit lengths for a BREAK error. Is it correct? Because 10x zeros is surely normal situation in our case.

    I hope you can further help us. Thank you.

    Kind regards,
    Gerald

  • 0 in reply to Gerald
    TI__Mastermind 26760 points

    Hi Gerald,

    Is the same frame: 0x00 byte (start-bit, 7x data=0, address bit=0, EVEN parity - totally 10 zeros) sent while the slave device is in WAKE or is this only sent when the device is in SLEEP mode? If it is also sent while the SCI slave is awake, are there any other errors being set such as framing error?

    Gerald said:
    As I see from the datasheet, BREAK time count starts after start-bit detection, so totally line must be in low-state during about 11x bit lengths for a BREAK error. Is it correct?

    I have forwarded this question to the design team. Most of the people are out of office though so I will reply as soon as I hear back which may be middle of next week. 

    Best Regards,

    Marlyn

  • 0 in reply to Marlyn Rosales Castaneda20
    TI__Genius 9570 points

    Hi Marlyn,

    Please be informed that I also received additional information from our customer in regards to your last response. Kindly see below:
    "Yes, similar frames are sent in both WAKE (addressed to this slave) and SLEEP (addressed to other slaves). There happened some other Rx error as well but we were in a big hurry to finalize the project so not sure what and when exactly.
    At the moment there is no hurry since I was forced to exclude SLEEP mode from operation. I can investigate the details later.
    Thank you for assistance."

    We will also wait for further update from you. Thank you again.

    Kind regards,
    Gerald

  • +1 in reply to Gerald
    TI__Mastermind 26760 points

    Hi Gerald,

    Thank you for that additional information. I suspect a framing error is occurring first when in WAKE followed by a break detect, but maybe the customer was just reading the framing error. In SLEEP the SCI module does not check for framing errors, only break detects are flagged.

    Yes, I will post an update once I hear back from design.

    Best Regards,

    Marlyn

  • 0 in reply to Marlyn Rosales Castaneda20
    TI__Genius 9570 points

    Hi Marlyn,

    Thanks for answer.
    According to our customer, hard to say but 2 things are sure:
    1. Customer do not use BREAK condition in the communication at all.
    2. But interrupt routine checks for Rx error flag and separately for a BREAK flag.
    There cannot be misdetection.

    Kind regards,
    Gerald