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TMS320F28377D: Read SCI FIFO.

Luke Chen
Expert 5090 points

Part Number: TMS320F28377D

Hi champs,

If we try to read out RX FIFO data and at the mean time RX shift register is transferring data into SCIRXBUF.

Is it possible we read out the data just been moved from shift register, not the data in FIFO?

Regards,

-Luke

  • +1
    TI__Mastermind 19795 points

    Hi Luke,

    Thanks for your question! When you read from the buffer (shift register), it always takes the First-In data. All other data that arrives while you read the buffer is still waiting in the buffer.

    It is not possible to directly read the other FIFO positions, so you can never accidentally read the data that just got shifted into the FIFO. You will always read the stable data from the buffer.

    Regards,

    Vince

  • 0 in reply to Vince
    TI__Expert 5090 points

    Vince,

    Based on my understanding, when we enable FIFO mode, the error bits SCIRXST.bit.FE and SCIRXST.bit.FE still work and will be saved into FIFO along with shift register data.

    Then we can use SCIRXBUF read out the data in FIFO, check the SCIFFFE and SCIFFPE bits to know what kind of error happened when this word was received, is my understanding correct please?

    -Luke

  • 0 in reply to Luke Chen
    TI__Mastermind 19795 points

    Hi Luke,

    You are correct! The SCIFFFE and SCIFFPE bits are set when the error occurs in the FIFO, not just when you read from the SCIRXBUF. So it will occur when the word was received as you mentioned.

    Regards,

    Vince

  • 0 in reply to Vince
    TI__Expert 5090 points

    Hi Vince,

    According to TRM, the FE and PE error bits can be reset by the SW RESET or system reset. So when the errors happen and users don't conduct SW RESET, then the FE and PE error bits will keep being saved into FIFO along with the data from RX shift register, is this correct?

    Because receive FIFO registers need to save FE and PE error bits, so there are 10-bit wide registers, right?

    Regards,

    Luke

  • 0 in reply to Luke Chen
    TI__Mastermind 19795 points

    Hi Luke,

    Just to avoid confusion, I want to clarify that there are two different sets of bits:

    EDIT+CORRECTION:Was able to confirm quickly that the SCIFFFE and SCIFFPE bits are stored per character in the FIFO, and so you are correct in your statement:

    Luke Chen said:
    Because receive FIFO registers need to save FE and PE error bits, so there are 10-bit wide registers, right?

    Regards,

    Vince

  • 0 in reply to Vince
    TI__Expert 5090 points

    Hi Vince,

    Below is my understanding, please correct me if there is anything wrong.

    Even in FIFO mode, the FE and PE bits of SCIRXST still work, means that SCI module sets FE bit when framing-error and sets PE bit when parity-error, then these two bits will be saved in FIFO with the data in RX shift register, it means that,

    T1: word1 received --> save word1, FE1 and PE1 into FIFO1.

    T2: word2 received --> save word2, FE2 and PE2 into FIFO2.

    T3: word3 received --> save word3, FE3 and PE3 into FIFO3 .... and so on.

    When customers use SCIRXBUF to read out FIFO data, they read out FIFO1 first, means that SAR field is word1, SCIFFFE is FE1 and SCIFFPE is PE1, then FIFO2 will be read out if customers read SCIRXBUF again, then FIFO3, and so on.

    In FIFO mode, SCI saves data into FIFO and SCIFFFE and SCIFFPE are the error bits(status) when word data was received, and this is the reason RX FIFO registers are 10-bit wide.

    Is my understanding correct please?

    Regards,

    Luke

  • 0 in reply to Luke Chen
    TI__Mastermind 19795 points

    Hi Luke,

    Your statements appear to be correct! Let me know if you have any follow-up questions.

    Regards,

    Vince

  • 0 in reply to Vince
    TI__Expert 5090 points

    Vince,

    From the E2E thread you provided, the customer wants to clear SCIFFFE and SCIFFPE bits in FIFO mode.

    https://e2e.ti.com/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/933753/tms320f280049-how-to-clear-scirxbuf/3463358#3463358

    I don't get the point well. If we say SCIFFFE and SCIFFPE bits are from FE and PE bits, used to indicate the error status at that time when data word was received in FIFO mode, customers don't need to clear these two bits, is it correct?

    Regards,

    Luke

  • 0 in reply to Luke Chen
    TI__Mastermind 19795 points

    Hi Luke,

    I believe the customer simply wanted to clear the error status from those bits, while relatively unnecessary. I will verify this, please expect a response by end of week.

    Regards,

    Vince

  • +1 in reply to Vince
    TI__Mastermind 19795 points

    Hi Luke,

    After discussing with design, in most cases, clearing of the SCIFFFE/SCIFFPE bits should not be necessary unless you are simply not wanting those error bits to be set for whatever reason.

    Since the FE/PE bits provide the same information, you can utilize those bits.

    Regards,

    Vince

  • 0 in reply to Vince
    TI__Expert 5090 points

    Vince,

    I see, thanks for all the details.

    Regards,

    Luke