TMS320F28069: Clearing trip-zone flags with DMA

Because DMA is supposed to have access to the ePWM registers, I assumed I could clear the cycle-by-cycle trip flags at CTR=0 using DMA. I set up DMA, use a static global in L5-L8 memory as source, and attempt to use EPwm4Regs.TZCLR as source, however this does not clear the flags. I checked the following things:

- When writing the global variable to TZCLR by software, the flags are cleared as expected

- When writing to a destination in L5-L8 RAM, the global variable is copied by DMA as expected

I have no idea what else I can check. Maybe it has something to do with the TZCLR register being EALLOW protected? Anyone with an idea what is going wrong here? I set up the channel with a function as follows:

int16 CopyNextCycle(Uint32 Src, Uint32 Dst, Uint16 Size)
{
    Uint16 ChNr = 0;
    while (ChannelsInUse[ChNr])
    {
        ChNr++;
        if (ChNr > 5) {
            return 1;
        }
    }
    ChannelsInUse[ChNr] = 1;

    GET_REG_LOCK;
    ChannelPtr[ChNr]->MODE.all = 0;
    ChannelPtr[ChNr]->MODE.bit.CONTINUOUS = 0;
    ChannelPtr[ChNr]->MODE.bit.PERINTE = 1;
    ChannelPtr[ChNr]->MODE.bit.PERINTSEL = 18;  // Triggered by PWM module 2 SoC A
    ChannelPtr[ChNr]->MODE.bit.CHINTE = 1;      // Generate interrupt (to mark channel as 'not anymore in use')
    ChannelPtr[ChNr]->MODE.bit.CHINTMODE = 1;   // Generate interrupt at end of transfer

    ChannelPtr[ChNr]->BURST_SIZE.all = Size;
    ChannelPtr[ChNr]->SRC_BURST_STEP = 1;
    ChannelPtr[ChNr]->DST_BURST_STEP = 1;
    ChannelPtr[ChNr]->TRANSFER_SIZE = 1;
    ChannelPtr[ChNr]->SRC_ADDR_SHADOW = Src;
    ChannelPtr[ChNr]->DST_ADDR_SHADOW = Dst;

    ChannelPtr[ChNr]->CONTROL.all = 0;
    ChannelPtr[ChNr]->CONTROL.bit.RUN = 1;
    RELEASE_REG_LOCK;

    return 0;
}

Then I call this function with the static variable as source, and the TZCLR register as destination, as follows:

CopyNextCycle((Uint32)&CbCTripFlagClear, (Uint32)&(EPwm4Regs.TZCLR), 1);