Part Number: TMS320F28388D
Other Parts Discussed in Thread: TMDSCNCD28388D, C2000WARE,
I hooked up a logic analyzer, and if I send an EtherCAT frame before the ESC is up and running, I can see the Ethernet frame show up in its entirety on the MII bus between the microcontroller and the PHY. This is the data from the Logic Analyzer:
55 55 55 55 55 55 55 d5 ff ff ff ff ff ff e4 b9 7a 3c f1 55 88 a4 0c 10 00 7f 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c8 ee 1e 8f
This is the data the EtherCAT master sent as seen by Wireshark, which matches the above data. It matches, except for the large numbers of zeros seen above (unclear why the frame is larger on MII than what Wireshark shows)
However, when I send a similar packet after I initialize the ESC, the frame is truncated and the "Invalid frame counter" field in the ESC register 0x300 increments when I send EtherCAT data from the PC/Master software. I'm able to see this register in a debug session.
The truncated frames look like this:
# frame stops mid-receive(?) 55 55 55 55 55 55 55 d5 // preamble + SFD ff ff ff ff ff ff // destination MAC e4 1f 1f 1f 1f // partial unknown source MAC # next frame: 55 55 55 55 55 55 55 d5 // preamble + SFD ff ff ff ff ff ff // destination MAC e4 1f 1f 1f 1f // partial unknown source MAC # next frame (same) 55 55 55 55 55 55 55 d5 // preamble + SFD ff ff ff ff ff ff // destination MAC e4 1f 1f 1f 1f // partial unknown source MAC
Schematics for reference
PHY (KSZ8061MNXI)
GPIO interface (same as Control Card TMDSCNCD28388D
