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TIDM-HV-1PH-DCAC: About the inverter duty cycle generation and normalized values

Part Number: TIDM-HV-1PH-DCAC
Other Parts Discussed in Thread: SFRA

HI

1.  In this design, i observed there is a mismatch in the design guide and the actual code.

In the design guide at build level 2:    invDuty PU = (invIoRefInst – invIoInst) × Gi/invVbusInst
In the code, at line 715                    :       invDutyPU= (gi_lead_lag_out + invVoInst)/  (invVbusInst*(VDCBUS_MAX_SENSE/VDC_NOMINAL));              

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(invIoRefInst – invIoInst) × Gi  is equal to  gi_lead_lag_out right?   So, what is the reason of the use of invVoInst in the code while design guide doesnt;

Also when extracting DC bus voltage, why use invVbusInst*(VDCBUS_MAX_SENSE/VDC_NOMINAL Instead of invVbusInst*VDCBUS_MAX_SENSE,  which is the correct way to extract the DC bus voltage from the PU values.
Also what is the difference of VDCBUS_MAX_SENSE and VDC_NOMINAL.

2.  In the Line 762 and 763, seems like the multipliers are used wrongly.

    guiVbus = invVbusInst*VAC_MAX_SENSE;
    guiVo = invVoInst*VDCBUS_MAX_SENSE;

As i understand, multipliers of above two should be interchanged, right?



Best Regards
Damith