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TMS320F28377S: Observed 3usec variation in timer0 isr

Part Number: TMS320F28377S

Dear All,

In our system we have 10MHz external oscillator

Sysclkout configured to 50 MHz. We observed @ Sysclkout GPIO= 49.1 to 51 MHz

Timer 0 configured to generate 100 µs:

#define SYSCLK 50000000

#define TIMER_CLK 1000000

#define TIMER_TIME 100

void TimerInit(void)

{

       Uint8 timer_prescal;

       CpuTimer0Regs.TCR.bit.TSS   = 1;

       timer_prescal               = SYSCLK/ TIMER_CLK

       CpuTimer0Regs.TPR.bit.TDDR  = timer_prescal;

       CpuTimer0Regs.TCR.bit.TIE   = 1;

       CpuTimer0Regs.TCR.bit.FREE  = 1;

       SetTimer(TIMER_TIME);    

       CpuTimer0Regs.TCR.bit.TSS   = 0;

}

 

void SetTimer(Uint32 time)

{

       Uint32 tmr_prd;

       tmr_prd = time;

      

       tmr_prd = (TIMER_CLK/1000000)*time;   

       CpuTimer0Regs.PRD.bit.LSW = tmr_prd & 0xFFFF;

       CpuTimer0Regs.PRD.bit.MSW = tmr_prd >> 16;   

}

For required 100 usec interrupt, we observed interrupt gets trigger at 103 usec.

What are possible reasons for observation and how to overcome same?

Regards....

Yogesh