TMS320F28377D: the CPU2 ePWM module can not work

Thanks for your reply.

According to your suggestion, I tried to set a 5s delay before the ePWM initialization in CPU2 for a simple test (using the same reference routine as above), but it didn’t work. The placement of the time delay is between InitPieVectTable(); and ConfigureADC();. Under normal circumstances, the 5s delay is sufficient to wait for CPU1 to complete initialization.

I also tried to use IPC to make CPU2 to wait for CPU1 initialization, but it didn’t work. The test code is shown below :

In CPU1, setting IPC10 flag in the last line before While(1) in the Main() function:

    EINT;

    ERTM;

    IpcRegs.IPCSET.bit.IPC10 = 1;

While(1)

{

;

}

In CPU2, using while() function to wait the IPC10 flag from CPU1:

#ifdef _FLASH

    memcpy(&RamfuncsRunStart, &RamfuncsLoadStart, (size_t)&RamfuncsLoadSize);

#endif

    InitSysCtrl();

#ifdef _FLASH

    InitFlash();

#endif

    while(IpcRegs.IPCSTS.bit.IPC10 != 1)

    {

        ;

    }

    IpcRegs.IPCACK.bit.IPC10 = 1;

Is there some faults when I use IPC to initialization? And is there some reference routine to solve this problems? Thanks for your attention.

Show me how you pass access to CPU2

The mainly modified parts of the reference routine are described above, and the reference routine is ti \ c2000 \ C2000Ware_3_04_00_00 \ device_support \ f2837xd \ examples \ dual \ adc_epwm. Other parts are kept the same as the original routine.

Can you share the small snippet of code showing how you pass the ownership?

In CPU1, the main part of the code is the same as the routine, and changes are highlighted in bold.

//

    InitEPwm1Gpio();

//

// Transfer ownership of EPWM1 and ADCA to CPU02

//

    EALLOW;

    DevCfgRegs.CPUSEL0.bit.EPWM1 = 1;

    DevCfgRegs.CPUSEL11.bit.ADC_A = 1;

    EDIS;

    IpcRegs.IPCSET.bit.IPC10 = 1;

//

// Step 6. IDLE loop. Just sit and loop forever (optional):

//

    while(1)

    {

        asm(" nop");

}

Did you pass the GPIO ownership to CPU2?

No. I am not going to use GPIO as output, so I have not configured it.

The core problem is: the routine works well when I chose “XXXRAM.cmd”, but the ePWM can not work well when I chose “XXXFLASH.cmd”. All changes were based in the routine “adc_epwm”, and the modified codes were shown in the past replies. I think if the ePWM can works well in the RAM or the DEBUG mode in the FLASH, the configured of ePWM is right.

I agree with your suggestion that the configuration of ePWM in CPU2 should wait for the finish of CPU1 initialization. So I tested this plan by set delay or IPC flag in CPU2 and the codes were shown in the above. The result is that the ePWM in CPU2 can be successfully configured sometimes by setting IPC flag, the failed times was about once or twice in 10 times when I quickly powered on and off. I think this phenomenon is due to the initialization of CPU2 being interrupted by other system’s ISR. I changed the placement of IPC10 flag in CPU2 to the first line after the function InitFlash(). Although it can reduce the fail times to some extent, the problem can not be solved completely.

Now I have to set a global flag in the ePWM’s ISR function and check it before the while(1) function in the main(). Once it is found that the global flag has not been update, the ePWM will be continually initialized. If the shared peripheral doesn’t need the corresponding ISR function (such as ADCEndISR, ePWMISR), this method can not be implemented.

Based on the above tests, I hope to have a stable method to ensure the ePWM or other shared peripherals can be initialized successfully in CPU2.

How many times do you spin in here?

 while(IpcRegs.IPCSTS.bit.IPC10 != 1)

    {

        ;

    }

Can you change it to 

 while(IpcRegs.IPCSTS.bit.IPC10 != 1)

    {

        count++;

    }

and see how many times you spin in this loop for the FAILED scenario?

Did you get the results?

Did you try this?