Part Number: TMS320F2809
Dear team:
In the ADC documentation Page 44, there are the following:
In the cascaded sequencer mode, registers ADCRESULT8 through ADCRESULT15 holds the results of the ninth through sixteenth conversions. The ADCRESULTn registers are left justified when read from Peripheral Frame 2 (0x7108-0x7117) with two wait states and right justified when read from Peripheral Frame 0 (0x0B00-0x0B0F) with zero wait states.
The customer finds that the address of his ADCRESULTn register is located in Peripheral Frame 2. How should I set it so that the address of the ADCRESULTn register is located in Peripheral Frame 0 (0x0B00-0x0B0F) to reduce 2 waiting cycles?
Best regards
