TMS320F28377D: CLA: C-to-assembly conversation

jawe477

Hello experts,

I am currently investigating the assembly language translation of the CLA C compiler and I don't understand something:

In the following C code	switch(uwA1) { case(4): uwB1++; uwA1 = 0; break; }
starts the assembler conversion with the following code:	00008b64: 7580994C MMOVZ16 MR0, @0x994c 00008b66: 78410000 MMOVIZ MR1, #0x0 00008b68: 7BC0003C MLSL32 MR0, 16 00008b6a: 78810004 MMOVXI MR1, #0x4 00008b6c: 7B80003C MLSR32 MR0, 16 00008b6e: 7F200001 MCMP32 MR1, MR0

1.) The 16Bit -UINT-variable "uwA1" is loaded with "MMOVZ16" into "MR0".
What are the following shift operations "MLSL32" and "MLSR32" for?
According to TRM the "MRa" register is loaded with "MMOVZ16" as follows:
MRa(31:16) = 0;
MRa(15:0) = [mem16];
So the shift operations seem unnecessary to me.
What am I missing?

2.) The comparison value "4" is loaded into "MR1". But before that "MR1" is reset to "0".
Why is this necessary?

Thanks in advance,

Jan

over 4 years ago

0 Ashwini Athalye over 4 years ago

TI__Expert 7715 points

Hi Jan,

I apologize for the delayed reply. I will circle back with the experts and let you know.

Can you let me know the optimization level in the settings?

Thanks,

Ashwini

0 Ashwini Athalye over 4 years ago in reply to Ashwini Athalye

TI__Expert 7715 points

Hi Jan,

jawe477 said:
The comparison value "4" is loaded into "MR1". But before that "MR1" is reset to "0".
Why is this necessary?

For immediate moves only 16-bits values can be specified. The MMOVXI only loads the lower 16-bit. The upper 16-bits need to be set to 0 which is accomplished by MOVIZ.

jawe477 said:
So the shift operations seem unnecessary to me.

Good point. I am reaching out to the compiler team for some insight here.

Thanks,

Ashwini

0 Ashwini Athalye over 4 years ago in reply to Ashwini Athalye

TI__Expert 7715 points

Hi Jan,

Please could you create a compiler test case for the first observation where shift instructions are being called. The steps are here:

http://software-dl.ti.com/ccs/esd/documents/sdto_cgt_How-to-Submit-a-Compiler-Test-Case.html

This will allow the compiler team to investigate.

Thanks,
Ashwini

0 jawe477 over 4 years ago in reply to Ashwini Athalye

Intellectual 700 points

Hi Ashwini,

thank you for your answer.

I'm sorry, but I can't create a compiler test case.

I am working on my own project and I am not allowed to release source code.

Unfortunately I don't have time to reproduce the problem with a sample project.

I am working with CCS version 10.4.0.00006 and the Compiler Version TI v20.2.5.LTS .

The output format is "legacy COFF" and I use the following optimization settings:

My actual goal is to program the CLA in assembler. To learn how to do this, I am investigating the translation of the C compiler.

As I said, I noticed the behavior with the shift operations.

My question was whether the shift operations are necessary or not and if so, why?

Regards,

Jan

+1 Ashwini Athalye over 4 years ago in reply to jawe477

TI__Expert 7715 points

Hi Jan,

Wish you a happy new year!

Thanks for the information, I will try and create a test case at my end.

The shift operations are unnecessary. As per the MMOVZ16 instruction details in the TRM, the upper 16-bits of MR0 will be zeroed out so the shifts should not be needed.

Thanks,

Ashwini

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TMS320F28377D: CLA: C-to-assembly conversation