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TMS320F28388D: Accessing ePWM registers from CPU2

inno
Expert 1700 points
Part Number: TMS320F28388D


Hi,

I am unable to access ePWM registers from CPU2.

For example, EPwm8Regs.TBPRD is set by CPU1, but I always read 0 from EPwm8Regs.TBPRD on CPU2. Even when CPU2 writes to EPwm8Regs.TBPRD, it reads back 0. EPwm8Regs.TBPRD is not EALLOW protected. I verified in run time that CPU2 tries to access memory location 0x0000_4763. Same results when using the debugger.

My understanding is that both CPU1 and CPU2 see the ePWM registers on the same memory location on their memory maps. Is it correct?

Please let me know how to access ePWM registers from CPU2 (if at all possible).

Thank you in advance.

Inno.

  • 0
    TI__Guru 52040 points

    You have to assign the peripheral to be OWNED by CPU2 if you want to use it on CPU2.

  • 0 in reply to Nima Eskandari
    Expert 1700 points

    1. Can you please direct me to a document (and section number) where I can find how to assign the peripheral to be owned by the different cores?

    2. Can CPU1 and CLA1 both access ePWM registers without switching ownership?

    Thanks,

    Inno.

  • 0 in reply to inno
    Expert 1700 points

    I found the answer to my first question. CPUSEL0 Register selects the EPWM modules ownership, where the only options are CPU1 and CPU2 (no CLA option). So my question is whether CPU1 and CLA1 can both access EPWM registers that are owned by CPU1?

    Thanks,

    Inno.

  • 0 in reply to inno
    TI__Guru 52040 points

    You select your owner between CPU1/CPU2.

    Then you have to provide the ACCESS control to either CPU, CLA or DMA.

    So one has access at a time but you can change the owner at run time.

    Nima

  • 0 in reply to Nima Eskandari
    Expert 1700 points

    Ok, thanks.

    How do I provide the access control to either CPU, CLA or DMA at run time?

    Thanks,

    Inno.

  • 0 in reply to inno
    TI__Guru 52040 points
    SysCtl_setPeripheralAccessControl(SYSCTL_ACCESS_EPWM1, 
            SYSCTL_ACCESS_CLA1, SYSCTL_ACCESS_FULL);
  • 0 in reply to Nima Eskandari
    Expert 1700 points

    The access control registers (e.g. EPWM1_AC Register) allow setting "full access for both read and write" independently for CLA1 and CPU1 (assuming the ownership is assigned to CPU1). Are there any restrictions to set "full access for both read and write" for CLA1 and CPU1 at the same time?

    Since there is CLA, DMA, and CPU Arbitration procedure, is it safe to set "full access for both read and write" for CLA1 and CPU1 at the same time and attempt to concurrently access a peripheral register within the same interface by CLA1 and CPU1?

    Thanks,

    Inno.

  • 0 in reply to inno
    TI__Guru 52040 points

    I believe that is the case and the arbitration takes care of it.

    can you confirm?

  • 0 in reply to Nima Eskandari
    Expert 1700 points

    The scheme that you attached refer to memory access arbitration. Is it applicable to peripheral access arbitration as well?

  • 0 in reply to inno
    TI__Guru** 115881 points

    Hi,

    inno said:
    The access control registers (e.g. EPWM1_AC Register) allow setting "full access for both read and write" independently for CLA1 and CPU1 (assuming the ownership is assigned to CPU1). Are there any restrictions to set "full access for both read and write" for CLA1 and CPU1 at the same time?

    There is no restriction.

    inno said:
    Since there is CLA, DMA, and CPU Arbitration procedure, is it safe to set "full access for both read and write" for CLA1 and CPU1 at the same time and attempt to concurrently access a peripheral register within the same interface by CLA1 and CPU1?

    It's safe or not depends on how application handles the error conditions. User need to provide access to each of them based on the requirement and if safety is critical in application then make sure there is proper procedure to handle any error.

    inno said:
    The scheme that you attached refer to memory access arbitration. Is it applicable to peripheral access arbitration as well?

    You are right. What has shared is for RAMs and for peripheral arbitration scheme is different. In case of peripheral, arbitration is based on fixed priority with DMA having highest priority then CLA and CPU at last. Also Write access has priority over Read.

    Hope this is clear.

    Regards,

    Vivek Singh

  • +1 in reply to Vivek Singh
    Expert 1700 points

    Thank you all for the support and clarifications. It helps me a lot.

    Inno.