TMS320F280025C: HIC using issue

Hi,

Regarding 1, Yes, this field blocks the external host's capability to write into the mailbox registers and the device region.

Regarding 2, Can you please elaborate on what do you mean by data is not consistent with the manual? Can you provide an example?

Regards,

Praveen

Hi Praveen,

Thanks for your support here!

Praveen Kumar Ravichandran said:

Regarding 1, Yes, this field blocks the external host's capability to write into the mailbox registers and the device region.

Is it different from the manual? The manual shows: a non-0xA value and can also write external host-writable registers in the HIC.

Praveen Kumar Ravichandran said:

Regarding 2, Can you please elaborate on what do you mean by data is not consistent with the manual? Can you provide an example?

For example, address 0x40 writes data, 0x44 writes data, and the first number is not packed, and the second number is outside the first number of the package address, triggering an error. The manual says to discard the first number of writes, but the actual test is retained.

Thanks and Best Regards,

Cherry

Hi Cherry,

I agree the manual is not very clear here. I will request for a documentation update here. In short, if the GCR holds a non-0xA value, the host will not have any access to the registers or device region. Thanks for pointing it out.

If I understand the second query right, when you try a non-consecutive address outside the packing boundary, you are seeing that the first write is still having effect instead of getting discarded?

Regards,

Praveen

Hi Praveen,

Sorry for the delay in feedback, I just hear back from the end customer today.

Praveen Kumar Ravichandran said:

when you try a non-consecutive address outside the packing boundary, you are seeing that the first write is still having effect instead of getting discarded?

Correct.

Can you share the Emif program that is paired with the 0025c routine?

The example demonstrates the following sequences
//! 1. Sending a message to the Host using Device to Host buffer,Passing a token
//! which triggers an interrupt at the Host.
//! 2. Waits for the Host to clear the interrupt.
//! 3. Then waits for a message from Host which contains the code 0x1 in
//! buffer index 0 and index 1 contains the Base address to be configured
//! 4. Configures the base address for Page 0
//! 5. Sends a message to Host after that is configured
//! 6. After this step the external host can use the address 0-0xFF
//! to access the Base address region in System memory

Is this a routine in mailbox mode? Can 0-FF access the peripheral space of 0025c?

Thanks and regards,

Cherry

Hi Cherry,

I will check with our experts to see if that is the expected behavior on packing scenario and get back.

Regarding the example, the c2000ware ex., 'hic_ex2_config_8bit_adc' uses the mailbox mode and its corresponding Emif code is situated inside '<C2000Ware InstallDir>\driverlib\f2838x\examples\c28x\emif\CCS\emif_ex8_8bit_asram_hic_adc'

As captured in the TRM & App note, in the mailbox mode, the access is restricted  only to the HIC register space. The host device's CPU or DMA is supposed to access the peripherals of interest and copy the data into/from the HIC mailbox registers.

Regards,

Praveen

Hi Praveen,

Thanks for your checking and expect your response!

Regards,

Cherry

Hi,

May I know is there any updates?

Thanks and regards,

Cherry

Cherry,

From our initial analysis, it seems like the first write doesnot get ignored. We are trying to confirm with internal simulations. We will get back in 2-3 days. Sorry for the delay

Regards,

Praveen

Hi Parveen,

Thanks and expect the updates.

Regards,

Cherry

Hi,

May I know is there anything new?

Thanks,

Cherry

Hi Cherry,

Apologies for the delay. We have re-created the scenario under different configs and we are observing that the first write will get ignored if the second write is outside the packing boundary.

We would like to understand more on the setup and the config to reproduce the exact scenario.

Can you please help us with the following:

1. The IO connections between the host and the device

2. The config options: HICMODECR, HICHOSTCR

3. The accesses that are placed from the host

Regards,

Praveen

Hi Praveen,

Thanks for your response.

Praveen Kumar Ravichandran said:

1. The IO connections between the host and the device

EMIF port connection, 8bits, per port signal connection relationship provided by TI documentation.

Praveen Kumar Ravichandran said:

2. The config options: HICMODECR, HICHOSTCR

MODECR=0xF40, HOSTCR is not configured.

Praveen Kumar Ravichandran said:

3. The accesses that are placed from the host

8bits-16bits pack: Write addresses 40, 41, 42, 44, 45, when will report error 44, 45 and 44. The lower 8 bits of the 16-bit data packaged in 45 and 44 are the number of 42. 

Write addresses 40, 42, 41, 43, no Error is reported, package 41 and 40, package 43 and 42.

Thanks and regards,

Cherry

Hi Cherry,

Thanks for the details. we will simulate these scenario and get back.

In the meanwhile, any reason to intentionally try these illegal sequences? The packing logic error feature was intended to catch any unintended miss during the application development

Regards,

Praveen

Hi Parveen,

Thanks and expect the updates.

Praveen Kumar Ravichandran said:

In the meanwhile, any reason to intentionally try these illegal sequences? The packing logic error feature was intended to catch any unintended miss during the application development

As you mentioned, they just want to know more about the tolerance of errors in order to design the system.

Thanks and regards,

Cherry

Hi Parveen,

May I know is there any update?

Thanks and regards,

Cherry

Hi Cherry,

Apologies for the delay, the team is busy with other milestones. I have requested a priority on this. I will let you know when we can have an update with the internal simulations

Regards,

Praveen

Hi Parveen,

Understood and thanks for your notice.

Best Regards,

Cherry

Hi Cherry,

Thanks for your patience. We did simulate and we are observing what you have mentioned.

When the sequence: 40,41,42,44,45 is initiated, the write 41 will get committed and packing is violated at address 44. The error & corresponding interrupt gets generated at this moment. The user is supposed to stop the further transaction on this error and any write beyond this point can lead to unintended writes as the state machine is in error condition already. In your case, since write to 45 is attempted beyond the point, it has caused an intended write with the data of 42.

Hope this clarifies the behavior.

Regards,

Praveen

Hi Parveen,

Thanks for your response.

Meaning it's not possible to tolerate errors? 

Regards,

Cherry

Hi Cherry,

In the sequence you mentioned, the packing is violated only when the address 0x44 is sent, and the error gets generated at this point. Hence the packing and error handling is working as expected. Do you agree?

Only the data that gets written is that of address 0x42, that is because the write of address 0x45 happens after the error condition and behavior is not guaranteed if there are accesses beyond error condition.

Regards,

Praveen