Part Number: TMS320F28388D
My application uses the TI TMS320F28388D with the Micron MT25q serial NOR flash memory connected to SPI-A. Assigned GPIO pins are:
GPIO16 = SPIA SIMO
GPIO17 = SPIA SOMI
GPIO18 = SPIA Clock
GPIO19 = SPIA Chip Select
GPIO98 = Device Write Protect
GPIO99 = Device Hold
GPIO 16-19 are reassigned to their SPI-A functions. GPIO 98 and 99 are programmed as GPIO Outputs.
For resource management reasons it is strongly preferred that the flash device run on CPU2. When I configure it to run on CPU1 it appears to work correctly, i.e. sending a Read Status Register command to the SPI results in correct activity on the SPI Clock, Chip Select and Data pins. However if I assign SPI-A and the two GPIO Outputs to CPU2, the GPIO Outputs (98 and 99) continue to work correctly but SPI-A does not... sending a Read Status Register command results in no activity on any of the SPI pins.
Below I have included the SPI Initialize function I use to set up the GPIO pins and transfer control to CPU2. This function is executed prior to CPU1 releasing CPU2's Reset so CPU2 can start. On the CPU2 side I don't do any additional configuration.
Something is missing here, probably something obvious, but I can't figure out what. Any assistance is greatly appreciated. And if you can point me to the TI documentation that explains it all, that would be even better... I am unable to find anything relevant in the 5000++ page user manual or 300+ page data sheet. At this point I am not even 100% certain that SPI-A can be run on CPU2 with these pin assignments, although I have not been able to find any indication that it cannot.
Sorry if the formatting / indentation is a bit off in the following source code, can't seem to figure out how to get "source code" formatting to work on this forum, also can't seem to get "preview" to work, hope the following source code comes out OK..
void FlashSpiInit( void )
{
// Program the SIMO pin (Slave Input Master Output)
//
GPIO_setMasterCore( 16, GPIO_CORE_CPU1 );
GPIO_setPinConfig( GPIO_16_SPISIMOA );
GPIO_setPadConfig( 16, GPIO_PIN_TYPE_PULLUP );
GPIO_setQualificationMode( 16, GPIO_QUAL_ASYNC );
// Program the SOMI pin (Slave Output Master Input)
//
GPIO_setMasterCore( 17, GPIO_CORE_CPU1 );
GPIO_setPinConfig( GPIO_17_SPISOMIA );
GPIO_setPadConfig( 17, GPIO_PIN_TYPE_PULLUP );
GPIO_setQualificationMode( 17, GPIO_QUAL_ASYNC );
// Program the Clock pin
//
GPIO_setMasterCore( 18, GPIO_CORE_CPU1 );
GPIO_setPinConfig( GPIO_18_SPICLKA );
GPIO_setPadConfig( 18, GPIO_PIN_TYPE_PULLUP );
GPIO_setQualificationMode( 18, GPIO_QUAL_ASYNC );
// Program the CS/STE pin
//
GPIO_setMasterCore( 19, GPIO_CORE_CPU1 );
GPIO_setPinConfig( GPIO_19_SPISTEA );
GPIO_setPadConfig( 19, GPIO_PIN_TYPE_PULLUP );
GPIO_setQualificationMode( 19, GPIO_QUAL_ASYNC );
// Program the Write Protect pin, leave it as a GPIO and make it an output
//
GPIO_setMasterCore( 98, GPIO_CORE_CPU1 );
GPIO_setPinConfig( GPIO_98_GPIO98 );
GPIO_setPadConfig( 98, GPIO_PIN_TYPE_PULLUP );
GPIO_setQualificationMode( 98, GPIO_QUAL_ASYNC );
GPIO_setDirectionMode( 98, GPIO_DIR_MODE_OUT );
// Program the Hold pin, leave it as a GPIO and make it an output
//
GPIO_setMasterCore( 99, GPIO_CORE_CPU1 );
GPIO_setPinConfig( GPIO_99_GPIO99 );
GPIO_setPadConfig( 99, GPIO_PIN_TYPE_PULLUP );
GPIO_setQualificationMode( 99, GPIO_QUAL_ASYNC );
GPIO_setDirectionMode( 99, GPIO_DIR_MODE_OUT );
SPI_disableModule( SPIA_BASE ); // Put SPI into reset before configuring
// SPI configuration. Use a 15MHz SPICLK and 8-bit word size.
//
SPI_setConfig( SPIA_BASE, DEVICE_LSPCLK_FREQ, SPI_PROT_POL1PHA0, SPI_MODE_MASTER, 15000000, 8 );
// FIFO configuration; associated interrupts will be enabled when other SPI
// interrupts are enabled
//
SPI_enableFIFO( SPIA_BASE );
SPI_resetTxFIFO( SPIA_BASE );
SPI_resetRxFIFO( SPIA_BASE );
SPI_enableModule( SPIA_BASE ); // Configuration complete. Release Reset to enable the module.
// All seem to work correctly when run on CPU1. If I execute the following
// to switch control to CPU2, the GPIO pins 98 and 99 work but the SPI
// device does not.
// I read on E2E that the GPIO pins that have been reassigned to SPI do not
// need to be reassigned to CPU2, only the GPIOs (WP and HOLD) and the SPI
// device need to be reassigned here. Tried both ways and didn't appear to
// make any difference.
//
GPIO_setMasterCore( 16, GPIO_CORE_CPU2 );
GPIO_setMasterCore( 17, GPIO_CORE_CPU2 );
GPIO_setMasterCore( 18, GPIO_CORE_CPU2 );
GPIO_setMasterCore( 19, GPIO_CORE_CPU2 );
GPIO_setMasterCore( 98, GPIO_CORE_CPU2 );
GPIO_setMasterCore( 99, GPIO_CORE_CPU2 );
SysCtl_selectCPUForPeripheral( SYSCTL_CPUSEL6_SPI, 1, SYSCTL_CPUSEL_CPU2 );
return;
}
