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TMS320F28379D: Debugging C1toC2 boot ROM supported IPCs

Sumit Panse
Prodigy 100 points

Part Number: TMS320F28379D

Hello team

I am trying to perform flash write operations on CPU2 flash using the boot ROM on CPU2 and I'm using IPCs to provide CPU2 boot ROM with 16-bit data to be flashed at given memory location. I know that we need WAIT_IN_BOOT mode for CPU2 core to have boot ROM IPCs supported, so, the flow which I have for now is as mentioned below:

- CPU1 boots-up to application.

- CPU1 resets CPU2 (using DevRegs for CPU2 reset)

- Wait for CPU2 to boot-up (monitoring IPCBOOTSTATUS for CPU2).

- Once CPU2 has booted-up, CPU1 provides memory addr, 16-bit data and IPC flahs for CMD and STATUS for flash write operation (as required for IPCLiteLtoRDataWrite function)

- Wait until we get ACK and written data (IPCLiteLtoRGetResult).

- Verify written data (from above step) with the actual data provided.

The problem which I am facing are:
1. I'm not sure on the debug configuration settings. For now, I have CPU1 loading the .out file for CPU1 only, but CPU1 and CPU2 are enabled to load symbols).

2. Is the flow (mentioned above) correct to perform a flash write using boot ROM for the slave core?

3. If the slave core already has something written at the memory address, is that cleared before writing to the same location (via boot ROM)? Or the boot ROM provides a different return in such cases?

Please help clearing the above mentioned problems.


Regards.

Sumit Panse

  • 0
    TI__Guru 50611 points

    Sumit,

    There is a simpler dual-core BlinkyLED example. You can first try that project to get familiar with flow. On CPU1, select CPU1_FLASH_STANDALONE and on CPU2, select CPU2_FLASH build configuration.

    Device_bootCPU2(C1C2_BROM_BOOTMODE_BOOT_FROM_FLASH) is used to boot CPU2 from flash.

    This example is very good to understand the boot flow from flash.

  • 0 in reply to Santosh Jha
    Prodigy 100 points

    Hi Santosh

    Thank you for the reply on the boot flow. Just FYI, I'm able to boot-up both cores already (in standalone and debug mode), the only concern is with getting CPU2 into WAIT_IN_BOOT state and on using boot-ROM of CPU2 for IPCs (these points highlighted below)

    Sumit Panse said:

    - Once CPU2 has booted-up, CPU1 provides memory addr, 16-bit data and IPC flahs for CMD and STATUS for flash write operation (as required for IPCLiteLtoRDataWrite function)

    - Wait until we get ACK and written data (IPCLiteLtoRGetResult).

    - Verify written data (from above step) with the actual data provided.

    Can you please help on these? Also, please help on confirming point 3 mentioned above:

    Sumit Panse said:
    3. If the slave core already has something written at the memory address, is that cleared before writing to the same location (via boot ROM)? Or the boot ROM provides a different return in such cases?


    Regards

    Sumit Panse

  • 0 in reply to Sumit Panse
    TI__Guru 50611 points

    Sumit,

    Have you gone through BBOT IPC section in TRM?

    Did you check CPU boot status for CPU2?

    Also checking "Section 4.9.10.3 CPU1 IPC NAK Status" and "Section4.9.10.4 CPU2 IPC NAK Status" may help you in narrowing the issue.

    https://www.ti.com/lit/ug/spruhm8h/spruhm8h.pdf