TMS320F28388D: DMA access HALT issue.

more information I want to share:

my task is using DMA CH1 continues read 512 16bit data from external EMIF CS2 and write 512 16 bit data to internal configured GS0 ram.

in the code, all INT disabled, all unused DMA Channels stoped. GS0 only configured for DMA write data, external EMIF CS2 only configured DMA read from. CPU only use internal RAM and ROM for operation.

the detailed DMA configuration as below.

/************************************************************************************************/

ramgs0 : > RAMGS0, type=NOINIT
ramgdma : > EMIF1_CS2n, type=NOINIT

/************************************************************************************************/

/************************************************************************************************/

#pragma DATA_SECTION(sData, "ramgs0"); // map the TX data to memory
#pragma DATA_SECTION(rData, "ramgdma"); // map the RX data to memory
uint16_t sData[512]; // Send data buffer
uint16_t rData[512]; // Receive data buffer
#define BURST 32 // write 8 to the register for a burst size of 8
#define TRANSFER 16 // [(MEM_BUFFER_SIZE/(BURST)]

/************************************************************************************************/

DMA_initController();
DEVICE_DELAY_US(500000);
const void *destAddr;
const void *srcAddr;
srcAddr = (const void *)rData;
destAddr = (const void *)sData;

//
// configure DMA CH6
//
DMA_configAddresses(DMA_CH1_BASE, destAddr, srcAddr);
DMA_configBurst(DMA_CH1_BASE,BURST,1,1);
DMA_configTransfer(DMA_CH1_BASE,TRANSFER,1,1);
DMA_configMode(DMA_CH1_BASE,DMA_TRIGGER_SOFTWARE, DMA_CFG_ONESHOT_ENABLE);//DMA_CFG_ONESHOT_ENABLE//DMA_CFG_ONESHOT_DISABLE
DMA_setEmulationMode(DMA_EMULATION_FREE_RUN);//DMA_EMULATION_STOP//DMA_EMULATION_FREE_RUN
// DMA_configWrap(DMA_CH1_BASE, 10, 1, 10, 1);
DMA_setPriorityMode(0);
DMA_stopChannel(DMA_CH2_BASE);
DMA_stopChannel(DMA_CH3_BASE);
DMA_stopChannel(DMA_CH4_BASE);
DMA_stopChannel(DMA_CH5_BASE);
DMA_stopChannel(DMA_CH6_BASE);

// DMA_setInterruptMode(DMA_CH1_BASE,DMA_INT_AT_END);
DMA_enableTrigger(DMA_CH1_BASE);

the oscilloscope shows that all 512 data should be transfered completed, but there are several halt around 200ns each during the access.

and I realized there are there type or HALT point from DMA state diagram in datasheet, but I have already try to set multi registers of the processor. not works

the picture with 3 HALTs was read data from CS2 and write to GS0

and picture with 6 HALTS was read data from GS0 and write to CS2.

appreciate any support.

thanks Vivek

I was using sram setting on EMIF1, and can you tell me more about the PD bit? what is the meaning of that?

That should power down the SDRAM logic. Just trying to see if there is any refresh command getting issued which is causing DMA access to be stalled.

Regards,

Vivek Singh

Hi Vivek

many thanks to you,after I use command"EMIF_enableSyncPowerDown(EMIF1_BASE);", there is no HALT any more.

so what is the root cause? in my program I only initiate the SRAM control register on EMIF. or register related to SDRAM keep default.

So I guess the halt should be trigered by EMIF controller.

I just saw this description from datasheet "The EMIF performs SDRAM refreshes even if the SDRAM interface is not used. If the user is using
only the ASRAM interface, then SDRAM refreshes will impact the ASRAM performance. To avoid this,
the user must set PD=1 in the SDRAM_CR register (Emif1Regs.SDRAM_CR.bit.PD=1). This bit can
be updated only if there are no pending EMIF accesses."