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TMS320F28377D: How to use the Digital Compare (DC) Submodule?

Lv Nemo
Prodigy 10 points
Part Number: TMS320F28377D
Other Parts Discussed in Thread: TEST2

As mentioned in the manual，in order to allow multiple comparators at a time to affect DCA/BEVTx events and trip actions, there is a OR logic to bring together ALL trip inputs (up to 15) from sources external to the ePWM module.In order to achieve this function, I configured the relevant registers and did experiments，through the test, I found the following phenomenon:

1)If the default polarity of the input signal is high and the abnormal polarity is low, then all signals need to be low to generate DCA/BEVTx events.This does not accord with the description in the manual.

2)If the signal default polarity is low and abnormal is high, then, one signal is high can generated DCA/BEVTx events.This is consistent with the description in the manual.

So, I would like to confirm whether the use of OR logic  requires polarity of input signals.

Looking forward to your reply.

  • 0
    TI__Mastermind 25240 points

    Hi Lv,

    Could you please provide the code you used to test 1 and 2 above? I can then use that to also test on my end and let you know whether the use of OR logic requires polarity of the input signals.

    Best Regards,

    Marlyn

  • 0 in reply to Marlyn Rosales Castaneda20
    Prodigy 10 points

    Hi Marlyn,
    thank you for your reply.The following is the code used in the tests:


    1)test1:(the default polarity of the input signal is high and the abnormal polarity is low)
    //config GPIO 33 and GPIO36
    GpioCtrlRegs.GPBGMUX1.bit.GPIO33 = 0;
    GpioCtrlRegs.GPBMUX1.bit.GPIO33 = 0;
    GpioCtrlRegs.GPBQSEL1.bit.GPIO33 = 0;
    GpioCtrlRegs.GPBPUD.bit.GPIO33 = 0;
    GpioCtrlRegs.GPBDIR.bit.GPIO33 = 0;

    GpioCtrlRegs.GPBGMUX1.bit.GPIO36 = 0;
    GpioCtrlRegs.GPBMUX1.bit.GPIO36 = 0;
    GpioCtrlRegs.GPBQSEL1.bit.GPIO36 = 0;
    GpioCtrlRegs.GPBPUD.bit.GPIO36 = 0;
    GpioCtrlRegs.GPBDIR.bit.GPIO36 = 0;

    //select GPIO 33 and GPIO 36 as input4 input 5
    InputXbarRegs.INPUT4SELECT = 33;
    InputXbarRegs.INPUT5SELECT = 36;

    InputXbarRegs.INPUTSELECTLOCK.bit.INPUT4SELECT = 1;
    InputXbarRegs.INPUTSELECTLOCK.bit.INPUT5SELECT = 1;

    //select input4 input5 as epwm trip4 trip5
    EpwmXbarRegs.TRIP4MUX0TO15CFG.bit.MUX7 = 1;
    EpwmXbarRegs.TRIP4MUXENABLE.bit.MUX7 = 1;

    EpwmXbarRegs.TRIP5MUX0TO15CFG.bit.MUX9 = 1;
    EpwmXbarRegs.TRIP5MUXENABLE.bit.MUX9 = 1;

    //config DC submodule
    Epwm1Regs->DCALTRIPSEL.bit.TRIPINPUT4 = 1;
    Epwm1Regs->DCALTRIPSEL.bit.TRIPINPUT5 = 1;
    Epwm1Regs->DCBLTRIPSEL.bit.TRIPINPUT4 = 1;
    Epwm1Regs->DCBLTRIPSEL.bit.TRIPINPUT5 = 1;
    Epwm1Regs->DCTRIPSEL.bit.DCALCOMPSEL = DC_COMBINATION;
    Epwm1Regs->DCTRIPSEL.bit.DCBLCOMPSEL = DC_COMBINATION;

    Epwm1Regs->TZDCSEL.bit.DCAEVT1 = TZ_DCAL_LOW;
    Epwm1Regs->TZDCSEL.bit.DCBEVT1 = TZ_DCBL_LOW;

    Epwm1Regs->TZSEL.bit.DCAEVT1 = TZ_ENABLE;
    Epwm1Regs->TZSEL.bit.DCBEVT1 = TZ_ENABLE;
    Epwm1Regs->TZCTL.bit.TZA = TZ_FORCE_LOW;
    Epwm1Regs->TZCTL.bit.TZB = TZ_FORCE_LOW;

    2)test2:(the default polarity of the input signal is low and the abnormal polarity is high)
    //config GPIO 33 and GPIO36
    GpioCtrlRegs.GPBGMUX1.bit.GPIO33 = 0;
    GpioCtrlRegs.GPBMUX1.bit.GPIO33 = 0;
    GpioCtrlRegs.GPBQSEL1.bit.GPIO33 = 0;
    GpioCtrlRegs.GPBPUD.bit.GPIO33 = 0;
    GpioCtrlRegs.GPBDIR.bit.GPIO33 = 0;

    GpioCtrlRegs.GPBGMUX1.bit.GPIO36 = 0;
    GpioCtrlRegs.GPBMUX1.bit.GPIO36 = 0;
    GpioCtrlRegs.GPBQSEL1.bit.GPIO36 = 0;
    GpioCtrlRegs.GPBPUD.bit.GPIO36 = 0;
    GpioCtrlRegs.GPBDIR.bit.GPIO36 = 0;

    //select GPIO 33 and GPIO 36 as input4 input 5
    InputXbarRegs.INPUT4SELECT = 33;
    InputXbarRegs.INPUT5SELECT = 36;

    InputXbarRegs.INPUTSELECTLOCK.bit.INPUT4SELECT = 1;
    InputXbarRegs.INPUTSELECTLOCK.bit.INPUT5SELECT = 1;

    //select input4 input5 as epwm trip4 trip5
    EpwmXbarRegs.TRIP4MUX0TO15CFG.bit.MUX7 = 1;
    EpwmXbarRegs.TRIP4MUXENABLE.bit.MUX7 = 1;

    EpwmXbarRegs.TRIP5MUX0TO15CFG.bit.MUX9 = 1;
    EpwmXbarRegs.TRIP5MUXENABLE.bit.MUX9 = 1;

    //config DC submodule
    Epwm1Regs->DCALTRIPSEL.bit.TRIPINPUT4 = 1;
    Epwm1Regs->DCALTRIPSEL.bit.TRIPINPUT5 = 1;
    Epwm1Regs->DCBLTRIPSEL.bit.TRIPINPUT4 = 1;
    Epwm1Regs->DCBLTRIPSEL.bit.TRIPINPUT5 = 1;
    Epwm1Regs->DCTRIPSEL.bit.DCALCOMPSEL = DC_COMBINATION;
    Epwm1Regs->DCTRIPSEL.bit.DCBLCOMPSEL = DC_COMBINATION;

    Epwm1Regs->TZDCSEL.bit.DCAEVT1 = TZ_DCAL_HI;
    Epwm1Regs->TZDCSEL.bit.DCBEVT1 = TZ_DCBL_HI;

    Epwm1Regs->TZSEL.bit.DCAEVT1 = TZ_ENABLE;
    Epwm1Regs->TZSEL.bit.DCBEVT1 = TZ_ENABLE;
    Epwm1Regs->TZCTL.bit.TZA = TZ_FORCE_LOW;
    Epwm1Regs->TZCTL.bit.TZB = TZ_FORCE_LOW;

    Thanks!

  • 0 in reply to Lv Nemo
    TI__Mastermind 25240 points

    Hi Lv,

    Thank you for providing the code. I have tested this on my side and I too see the same outcome as you. I will conduct some further testing to see if the design implementation is indeed designed for this and if so I will be updating the documentation to reflect this. I'll keep you posted with any findings as soon as I get them.

    Best Regards,

    Marlyn

  • 0 in reply to Marlyn Rosales Castaneda20
    Prodigy 10 points

    Hi Marlyn,

    Thank you for your quick reply and look forward to the final test results.

  • +1 in reply to Lv Nemo
    TI__Mastermind 25240 points

    Hi Lv,

    The behavior you observed is actually the intended behavior. I will be updating our collateral to reflect this.

    Best Regards,

    Marlyn

  • 0 in reply to Marlyn Rosales Castaneda20
    Prodigy 10 points

    Hi Marlyn,

    Thank you for this useful information.This result is very important for us, which decides whether to modify the design. Thank you again for your hard work.

    Regards,

    Lv