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TMS320F280023C: Watchdog stops triggering

Part Number: TMS320F280023C
Other Parts Discussed in Thread: SYSCONFIG, LAUNCHXL-F280025C

Hi

I have setup the watchdog to trigger after 209 mS.

So far I have _NOT_ setup any servicing of the watchdog, so it should just re-reset my device in Infinity, or to i pull the plug.

And indeed after first powerup it resets the device, and continuous to do so for some time, but then it stops doing that.

First i thought the device was stuck in some NMI or exception of some sort. But it turns out it is running fine, and my application code is running as if no watchdog present.

So in short

Exspected:

Device reset every 209 mS until power is removed.

Reality:

Device reset every 209 mS for some time then the reset event stops, and the cpu runs normal SW.

"some time" = variable time frm 2 seconds to 20 seconds approximately.

The watchdog is set using the Sysconfig tool:

With 209 mS run time it is plenty time to print out some debug information on my serial port.

So I added this just after serial init

    Log_debug("WatchDog counter value = %u\r\n", SysCtl_getWatchdogCounterValue());
    Log_debug("WatchDog reset status = %d\r\n", SysCtl_getWatchdogResetStatus());
    Log_debug("Sys control and status register = %X\r\n", HWREGH(WD_BASE + SYSCTL_O_SCSR));
    Log_debug("WatchDog KEY register = %X\r\n", HWREGH(WD_BASE + SYSCTL_O_WDKEY));
    Log_debug("WatchDog status register = %X\r\n", HWREGH(WD_BASE + SYSCTL_O_WDCR));
    Log_debug("WatchDog Windowed status register = %X\r\n", HWREGH(WD_BASE + SYSCTL_O_WDWCR));
    

* Log_debug is just  macro expanding in to printf

From that I get

DBG: WatchDog counter value = 1
DBG: WatchDog reset status = 0
DBG: Sys control and status register = 5
DBG: WatchDog KEY register = 7
DBG: WatchDog status register = E07
DBG: WatchDog Windowed status register = 0

This show the same  values both when a reset is later triggered and when not.

I also have these values printed on command in my testmonitor, and when I ask for them after the reset stopped happening I still get the same values except for the counter that keeps changing (indicating that it is running)

So why do my watchdog stop working?

  • Hi,

    Can you post the WD initialization code also here. Also when WD stop firing reset, is there any activity on IOs through which you can confirm that application (your code) is still running. if not then just add a GPIO toggle code in while 1 loop after WD initialization to confirm the same. It could also be possible that after reset, device is not booting properly hence it never does the WD initialization. Is this TI board or your own customer board ? And do you have any active driver on device BOOT PINs ? 

    Regards,

    Vivek Singh

  • 1. initialization code in the sysconfig generated code (using latest sysconfig 4.0).

    void WATCHDOG_init(){
    	//WATCHDOG initialization 
    	SysCtl_disableWatchdog();
    	SysCtl_setWatchdogMode(SYSCTL_WD_MODE_RESET);
    	SysCtl_setWatchdogPredivider(SYSCTL_WD_PREDIV_128);
    	SysCtl_setWatchdogPrescaler(SYSCTL_WD_PRESCALE_64);
    	SysCtl_setWatchdogWindowValue(0);
    	SysCtl_enableWatchdog();
    	
    	 	
    }
    

    2.

    I have lots of io activity, amongst my test-monitor running on the serial port. Here is a sample of the communication that copied from my serial terminal, so you see the application code is very much alive.

    test>pm,r,d
    
    DBG: WatchDog counter value = 20
    DBG: WatchDog reset status = 0
    DBG: Sys control and status register = 5
    DBG: WatchDog KEY register = 7
    DBG: WatchDog status register = E07
    DBG: WatchDog Windowed status register = 0
    
    
    test>pm,r,d
    
    DBG: WatchDog counter value = 148
    DBG: WatchDog reset status = 0
    DBG: Sys control and status register = 5
    DBG: WatchDog KEY register = 7
    DBG: WatchDog status register = E07
    DBG: WatchDog Windowed status register = 0

    3.

    Yes the WD initialization is being run Or else I would not see the correct values being printed by log_debug on serial terminal just after boot, as i quoted in my question.

    Also as you can see in the above snippet from my test-monitor all the values from watchdog init is still there.

    4.

    This is our custom board.

    5.

    There is a pull-up on GPIO32 and GPIO24, but if you still question if init and application actually running, because it went in to another boot mode, then no it enters flash mode and runs the init and application as described above, also this was my first thought and i ruled that out very early.

    First i thought the device was stuck in some NMI or exception of some sort. But it turns out it is running fine, and my application code is running as if no watchdog present.
  • Ok, so you have two two back to back WD count value and count value is changing. It means WD is counting. If you keep printing these value, do you se WD count maxout ever and what happens after that ?

  • Also can you confirm that you have all the code in flash only and not in RAM.

  • Only the setting of flash wait states code is in ramfuncs.

  • Yes counter is running as I stated inthe original answer, and nothing happens when the counter wraps.

    Attaching a longer log from terminal with timestamps so you can see.

    And as i also mentioned I have not even implemented any servicing of the watchdog, so it is not being reset by my SW anywhere.

    [2022-01-08 01:01:23.987] pm,r,d
    [2022-01-08 01:01:26.066] 
    [2022-01-08 01:01:26.066] DBG: WatchDog counter value = 16
    [2022-01-08 01:01:26.072] DBG: WatchDog reset status = 0
    [2022-01-08 01:01:26.072] DBG: Sys control and status register = 5
    [2022-01-08 01:01:26.072] DBG: WatchDog KEY register = 7
    [2022-01-08 01:01:26.072] DBG: WatchDog status register = E07
    [2022-01-08 01:01:26.072] DBG: WatchDog Windowed status register = 0
    [2022-01-08 01:01:26.088] 
    [2022-01-08 01:01:26.088] 
    [2022-01-08 01:01:26.088] test>pm,r,d
    [2022-01-08 01:01:26.872] 
    [2022-01-08 01:01:26.872] DBG: WatchDog counter value = 1
    [2022-01-08 01:01:26.872] DBG: WatchDog reset status = 0
    [2022-01-08 01:01:26.888] DBG: Sys control and status register = 5
    [2022-01-08 01:01:26.896] DBG: WatchDog KEY register = 7
    [2022-01-08 01:01:26.896] DBG: WatchDog status register = E07
    [2022-01-08 01:01:26.899] DBG: WatchDog Windowed status register = 0
    [2022-01-08 01:01:26.904] 
    [2022-01-08 01:01:26.905] 
    [2022-01-08 01:01:26.905] test>pm,r,d
    [2022-01-08 01:01:27.522] 
    [2022-01-08 01:01:27.522] DBG: WatchDog counter value = 25
    [2022-01-08 01:01:27.522] DBG: WatchDog reset status = 0
    [2022-01-08 01:01:27.522] DBG: Sys control and status register = 5
    [2022-01-08 01:01:27.522] DBG: WatchDog KEY register = 7
    [2022-01-08 01:01:27.522] DBG: WatchDog status register = E07
    [2022-01-08 01:01:27.538] DBG: WatchDog Windowed status register = 0
    [2022-01-08 01:01:27.538] 
    [2022-01-08 01:01:27.538] 
    [2022-01-08 01:01:27.538] test>pm,r,d
    [2022-01-08 01:01:28.155] 
    [2022-01-08 01:01:28.155] DBG: WatchDog counter value = 38
    [2022-01-08 01:01:28.155] DBG: WatchDog reset status = 0
    [2022-01-08 01:01:28.155] DBG: Sys control and status register = 5
    [2022-01-08 01:01:28.165] DBG: WatchDog KEY register = 7
    [2022-01-08 01:01:28.165] DBG: WatchDog status register = E07
    [2022-01-08 01:01:28.171] DBG: WatchDog Windowed status register = 0
    [2022-01-08 01:01:28.171] 
    [2022-01-08 01:01:28.171] 
    [2022-01-08 01:01:28.171] test>pm,r,d
    [2022-01-08 01:01:28.803] 
    [2022-01-08 01:01:28.803] DBG: WatchDog counter value = 80
    [2022-01-08 01:01:28.803] DBG: WatchDog reset status = 0
    [2022-01-08 01:01:28.803] DBG: Sys control and status register = 5
    [2022-01-08 01:01:28.818] DBG: WatchDog KEY register = 7
    [2022-01-08 01:01:28.822] DBG: WatchDog status register = E07
    [2022-01-08 01:01:28.822] DBG: WatchDog Windowed status register = 0
    [2022-01-08 01:01:28.822] 
    [2022-01-08 01:01:28.822] 
    [2022-01-08 01:01:28.822] test>pm,r,d
    [2022-01-08 01:01:29.486] 
    [2022-01-08 01:01:29.486] DBG: WatchDog counter value = 166
    [2022-01-08 01:01:29.502] DBG: WatchDog reset status = 0
    [2022-01-08 01:01:29.505] DBG: Sys control and status register = 5
    [2022-01-08 01:01:29.505] DBG: WatchDog KEY register = 7
    [2022-01-08 01:01:29.505] DBG: WatchDog status register = E07
    [2022-01-08 01:01:29.505] DBG: WatchDog Windowed status register = 0
    [2022-01-08 01:01:29.522] 
    [2022-01-08 01:01:29.522] 
    [2022-01-08 01:01:29.522] test>pm,r,d
    [2022-01-08 01:01:30.105] 
    [2022-01-08 01:01:30.105] DBG: WatchDog counter value = 158
    [2022-01-08 01:01:30.105] DBG: WatchDog reset status = 0
    [2022-01-08 01:01:30.121] DBG: Sys control and status register = 5
    [2022-01-08 01:01:30.121] DBG: WatchDog KEY register = 7
    [2022-01-08 01:01:30.121] DBG: WatchDog status register = E07
    [2022-01-08 01:01:30.121] DBG: WatchDog Windowed status register = 0
    [2022-01-08 01:01:30.137] 
    [2022-01-08 01:01:30.137] 
    [2022-01-08 01:01:30.137] test>pm,r,d
    [2022-01-08 01:01:30.738] 
    [2022-01-08 01:01:30.738] DBG: WatchDog counter value = 163
    [2022-01-08 01:01:30.738] DBG: WatchDog reset status = 0
    [2022-01-08 01:01:30.738] DBG: Sys control and status register = 5
    [2022-01-08 01:01:30.738] DBG: WatchDog KEY register = 7
    [2022-01-08 01:01:30.738] DBG: WatchDog status register = E07
    [2022-01-08 01:01:30.755] DBG: WatchDog Windowed status register = 0
    [2022-01-08 01:01:30.755] 
    [2022-01-08 01:01:30.755] 
    [2022-01-08 01:01:30.755] test>pm,r,d
    [2022-01-08 01:01:31.404] 
    [2022-01-08 01:01:31.404] DBG: WatchDog counter value = 215
    [2022-01-08 01:01:31.405] DBG: WatchDog reset status = 0
    [2022-01-08 01:01:31.405] DBG: Sys control and status register = 5
    [2022-01-08 01:01:31.405] DBG: WatchDog KEY register = 7
    [2022-01-08 01:01:31.405] DBG: WatchDog status register = E07
    [2022-01-08 01:01:31.405] DBG: WatchDog Windowed status register = 0
    [2022-01-08 01:01:31.422] 
    [2022-01-08 01:01:31.422] 
    [2022-01-08 01:01:31.422] test>pm,r,d
    [2022-01-08 01:01:32.015] 
    [2022-01-08 01:01:32.015] DBG: WatchDog counter value = 209
    [2022-01-08 01:01:32.023] DBG: WatchDog reset status = 0
    [2022-01-08 01:01:32.025] DBG: Sys control and status register = 5
    [2022-01-08 01:01:32.025] DBG: WatchDog KEY register = 7
    [2022-01-08 01:01:32.025] DBG: WatchDog status register = E07
    [2022-01-08 01:01:32.035] DBG: WatchDog Windowed status register = 0
    [2022-01-08 01:01:32.038] 
    [2022-01-08 01:01:32.038] 
    [2022-01-08 01:01:32.038] test>pm,r,d
    [2022-01-08 01:01:32.663] 
    [2022-01-08 01:01:32.663] DBG: WatchDog counter value = 243
    [2022-01-08 01:01:32.671] DBG: WatchDog reset status = 0
    [2022-01-08 01:01:32.673] DBG: Sys control and status register = 5
    [2022-01-08 01:01:32.673] DBG: WatchDog KEY register = 7
    [2022-01-08 01:01:32.673] DBG: WatchDog status register = E07
    [2022-01-08 01:01:32.683] DBG: WatchDog Windowed status register = 0
    [2022-01-08 01:01:32.683] 
    [2022-01-08 01:01:32.683] 
    [2022-01-08 01:01:32.683] test>pm,r,d
    [2022-01-08 01:01:33.278] 
    [2022-01-08 01:01:33.278] DBG: WatchDog counter value = 237
    [2022-01-08 01:01:33.286] DBG: WatchDog reset status = 0
    [2022-01-08 01:01:33.288] DBG: Sys control and status register = 5
    [2022-01-08 01:01:33.288] DBG: WatchDog KEY register = 7
    [2022-01-08 01:01:33.288] DBG: WatchDog status register = E07
    [2022-01-08 01:01:33.298] DBG: WatchDog Windowed status register = 0
    [2022-01-08 01:01:33.305] 
    [2022-01-08 01:01:33.305] 
    [2022-01-08 01:01:33.305] test>pm,r,d
    [2022-01-08 01:01:33.888] 
    [2022-01-08 01:01:33.888] DBG: WatchDog counter value = 221
    [2022-01-08 01:01:33.888] DBG: WatchDog reset status = 0
    [2022-01-08 01:01:33.888] DBG: Sys control and status register = 5
    [2022-01-08 01:01:33.888] DBG: WatchDog KEY register = 7
    [2022-01-08 01:01:33.904] DBG: WatchDog status register = E07
    [2022-01-08 01:01:33.904] DBG: WatchDog Windowed status register = 0
    [2022-01-08 01:01:33.904] 
    [2022-01-08 01:01:33.904] 
    [2022-01-08 01:01:33.904] test>pm,r,d
    [2022-01-08 01:01:34.613] 
    [2022-01-08 01:01:34.613] DBG: WatchDog counter value = 87
    [2022-01-08 01:01:34.613] DBG: WatchDog reset status = 0
    [2022-01-08 01:01:34.613] DBG: Sys control and status register = 5
    [2022-01-08 01:01:34.622] DBG: WatchDog KEY register = 7
    [2022-01-08 01:01:34.623] DBG: WatchDog status register = E07
    [2022-01-08 01:01:34.623] DBG: WatchDog Windowed status register = 0
    [2022-01-08 01:01:34.631] 
    [2022-01-08 01:01:34.631] 
    [2022-01-08 01:01:34.631] test>pm,r,d
    [2022-01-08 01:01:35.267] 
    [2022-01-08 01:01:35.267] DBG: WatchDog counter value = 131
    [2022-01-08 01:01:35.269] DBG: WatchDog reset status = 0
    [2022-01-08 01:01:35.272] DBG: Sys control and status register = 5
    [2022-01-08 01:01:35.277] DBG: WatchDog KEY register = 7
    [2022-01-08 01:01:35.277] DBG: WatchDog status register = E07
    [2022-01-08 01:01:35.277] DBG: WatchDog Windowed status register = 0
    [2022-01-08 01:01:35.287] 
    [2022-01-08 01:01:35.287] 
    [2022-01-08 01:01:35.287] test>pm,r,d
    [2022-01-08 01:01:35.924] 
    [2022-01-08 01:01:35.924] DBG: WatchDog counter value = 174
    [2022-01-08 01:01:35.926] DBG: WatchDog reset status = 0
    [2022-01-08 01:01:35.926] DBG: Sys control and status register = 5
    [2022-01-08 01:01:35.926] DBG: WatchDog KEY register = 7
    [2022-01-08 01:01:35.934] DBG: WatchDog status register = E07
    [2022-01-08 01:01:35.938] DBG: WatchDog Windowed status register = 0
    [2022-01-08 01:01:35.946] 
    [2022-01-08 01:01:35.946] 
    [2022-01-08 01:01:35.946] test>pm,r,d
    [2022-01-08 01:01:36.562] 
    [2022-01-08 01:01:36.562] DBG: WatchDog counter value = 198
    [2022-01-08 01:01:36.562] DBG: WatchDog reset status = 0
    [2022-01-08 01:01:36.570] DBG: Sys control and status register = 5
    [2022-01-08 01:01:36.572] DBG: WatchDog KEY register = 7
    [2022-01-08 01:01:36.572] DBG: WatchDog status register = E07
    [2022-01-08 01:01:36.580] DBG: WatchDog Windowed status register = 0
    [2022-01-08 01:01:36.582] 
    [2022-01-08 01:01:36.582] 
    [2022-01-08 01:01:36.582] test>pm,r,d
    [2022-01-08 01:01:37.171] 
    [2022-01-08 01:01:37.171] DBG: WatchDog counter value = 191
    [2022-01-08 01:01:37.171] DBG: WatchDog reset status = 0
    [2022-01-08 01:01:37.171] DBG: Sys control and status register = 5
    [2022-01-08 01:01:37.188] DBG: WatchDog KEY register = 7
    [2022-01-08 01:01:37.188] DBG: WatchDog status register = E07
    [2022-01-08 01:01:37.188] DBG: WatchDog Windowed status register = 0
    [2022-01-08 01:01:37.188] 
    [2022-01-08 01:01:37.188] 
    [2022-01-08 01:01:37.188] test>pm,r,d
    [2022-01-08 01:01:37.835] 
    [2022-01-08 01:01:37.835] DBG: WatchDog counter value = 235
    [2022-01-08 01:01:37.838] DBG: WatchDog reset status = 0
    [2022-01-08 01:01:37.843] DBG: Sys control and status register = 5
    [2022-01-08 01:01:37.845] DBG: WatchDog KEY register = 7
    [2022-01-08 01:01:37.845] DBG: WatchDog status register = E07
    [2022-01-08 01:01:37.853] DBG: WatchDog Windowed status register = 0
    [2022-01-08 01:01:37.856] 
    [2022-01-08 01:01:37.856] 
    [2022-01-08 01:01:37.856] test>pm,r,d
    [2022-01-08 01:01:38.467] 
    [2022-01-08 01:01:38.467] DBG: WatchDog counter value = 249
    [2022-01-08 01:01:38.472] DBG: WatchDog reset status = 0
    [2022-01-08 01:01:38.472] DBG: Sys control and status register = 5
    [2022-01-08 01:01:38.475] DBG: WatchDog KEY register = 7
    [2022-01-08 01:01:38.475] DBG: WatchDog status register = E07
    [2022-01-08 01:01:38.475] DBG: WatchDog Windowed status register = 0
    [2022-01-08 01:01:38.485] 
    [2022-01-08 01:01:38.485] 
    [2022-01-08 01:01:38.485] test>pm,r,d
    [2022-01-08 01:01:39.107] 
    [2022-01-08 01:01:39.107] DBG: WatchDog counter value = 25
    [2022-01-08 01:01:39.117] DBG: WatchDog reset status = 0
    [2022-01-08 01:01:39.121] DBG: Sys control and status register = 5
    [2022-01-08 01:01:39.121] DBG: WatchDog KEY register = 7
    [2022-01-08 01:01:39.121] DBG: WatchDog status register = E07
    [2022-01-08 01:01:39.121] DBG: WatchDog Windowed status register = 0
    [2022-01-08 01:01:39.121] 
    [2022-01-08 01:01:39.121] 
    [2022-01-08 01:01:39.121] test>pm,r,d
    [2022-01-08 01:01:39.738] 
    [2022-01-08 01:01:39.738] DBG: WatchDog counter value = 29
    [2022-01-08 01:01:39.738] DBG: WatchDog reset status = 0
    [2022-01-08 01:01:39.738] DBG: Sys control and status register = 5
    [2022-01-08 01:01:39.738] DBG: WatchDog KEY register = 7
    [2022-01-08 01:01:39.738] DBG: WatchDog status register = E07
    [2022-01-08 01:01:39.755] DBG: WatchDog Windowed status register = 0
    [2022-01-08 01:01:39.755] 
    [2022-01-08 01:01:39.755] 
    [2022-01-08 01:01:39.755] test>pm,r,d
    [2022-01-08 01:01:40.321] 
    [2022-01-08 01:01:40.321] DBG: WatchDog counter value = 241
    [2022-01-08 01:01:40.321] DBG: WatchDog reset status = 0
    [2022-01-08 01:01:40.321] DBG: Sys control and status register = 5
    [2022-01-08 01:01:40.321] DBG: WatchDog KEY register = 7
    [2022-01-08 01:01:40.338] DBG: WatchDog status register = E07
    [2022-01-08 01:01:40.338] DBG: WatchDog Windowed status register = 0
    [2022-01-08 01:01:40.355] 
    [2022-01-08 01:01:40.355] 
    [2022-01-08 01:01:40.355] test>pm,r,d
    [2022-01-08 01:01:40.938] 
    [2022-01-08 01:01:40.938] DBG: WatchDog counter value = 245
    [2022-01-08 01:01:40.938] DBG: WatchDog reset status = 0
    [2022-01-08 01:01:40.955] DBG: Sys control and status register = 5
    [2022-01-08 01:01:40.955] DBG: WatchDog KEY register = 7
    [2022-01-08 01:01:40.955] DBG: WatchDog status register = E07
    [2022-01-08 01:01:40.955] DBG: WatchDog Windowed status register = 0
    [2022-01-08 01:01:40.955] 
    [2022-01-08 01:01:40.955] 
    [2022-01-08 01:01:40.955] test>pm,r,d
    [2022-01-08 01:01:41.555] 
    [2022-01-08 01:01:41.555] DBG: WatchDog counter value = 229
    [2022-01-08 01:01:41.569] DBG: WatchDog reset status = 0
    [2022-01-08 01:01:41.571] DBG: Sys control and status register = 5
    [2022-01-08 01:01:41.571] DBG: WatchDog KEY register = 7
    [2022-01-08 01:01:41.571] DBG: WatchDog status register = E07
    [2022-01-08 01:01:41.571] DBG: WatchDog Windowed status register = 0
    [2022-01-08 01:01:41.577] 
    [2022-01-08 01:01:41.577] 
    [2022-01-08 01:01:41.577] test>pm,r,d
    [2022-01-08 01:01:42.221] 
    [2022-01-08 01:01:42.221] DBG: WatchDog counter value = 26
    [2022-01-08 01:01:42.223] DBG: WatchDog reset status = 0
    [2022-01-08 01:01:42.223] DBG: Sys control and status register = 5
    [2022-01-08 01:01:42.238] DBG: WatchDog KEY register = 7
    [2022-01-08 01:01:42.238] DBG: WatchDog status register = E07
    [2022-01-08 01:01:42.238] DBG: WatchDog Windowed status register = 0
    [2022-01-08 01:01:42.241] 
    [2022-01-08 01:01:42.241] 
    [2022-01-08 01:01:42.241] test>pm,r,d
    [2022-01-08 01:01:42.828] 
    [2022-01-08 01:01:42.828] DBG: WatchDog counter value = 10
    [2022-01-08 01:01:42.828] DBG: WatchDog reset status = 0
    [2022-01-08 01:01:42.828] DBG: Sys control and status register = 5
    [2022-01-08 01:01:42.836] DBG: WatchDog KEY register = 7
    [2022-01-08 01:01:42.838] DBG: WatchDog status register = E07
    [2022-01-08 01:01:42.855] DBG: WatchDog Windowed status register = 0
    [2022-01-08 01:01:42.858] 
    [2022-01-08 01:01:42.858] 
    [2022-01-08 01:01:42.858] test>pm,r,d
    [2022-01-08 01:01:43.455] 
    [2022-01-08 01:01:43.455] DBG: WatchDog counter value = 24
    [2022-01-08 01:01:43.455] DBG: WatchDog reset status = 0
    [2022-01-08 01:01:43.455] DBG: Sys control and status register = 5
    [2022-01-08 01:01:43.455] DBG: WatchDog KEY register = 7
    [2022-01-08 01:01:43.472] DBG: WatchDog status register = E07
    [2022-01-08 01:01:43.472] DBG: WatchDog Windowed status register = 0
    [2022-01-08 01:01:43.488] 
    [2022-01-08 01:01:43.488] 
    [2022-01-08 01:01:43.488] test>pm,r,d
    [2022-01-08 01:01:44.072] 
    [2022-01-08 01:01:44.072] DBG: WatchDog counter value = 19
    [2022-01-08 01:01:44.072] DBG: WatchDog reset status = 0
    [2022-01-08 01:01:44.072] DBG: Sys control and status register = 5
    [2022-01-08 01:01:44.087] DBG: WatchDog KEY register = 7
    [2022-01-08 01:01:44.088] DBG: WatchDog status register = E07
    [2022-01-08 01:01:44.088] DBG: WatchDog Windowed status register = 0
    [2022-01-08 01:01:44.109] 
    [2022-01-08 01:01:44.109] 
    [2022-01-08 01:01:44.109] test>pm,r,d
    [2022-01-08 01:01:44.659] 
    [2022-01-08 01:01:44.659] DBG: WatchDog counter value = 238
    [2022-01-08 01:01:44.671] DBG: WatchDog reset status = 0
    [2022-01-08 01:01:44.671] DBG: Sys control and status register = 5
    [2022-01-08 01:01:44.688] DBG: WatchDog KEY register = 7
    [2022-01-08 01:01:44.688] DBG: WatchDog status register = E07
    [2022-01-08 01:01:44.688] DBG: WatchDog Windowed status register = 0
    [2022-01-08 01:01:44.688] 
    [2022-01-08 01:01:44.688] 
    [2022-01-08 01:01:44.688] test>pm,r,d
    [2022-01-08 01:01:45.321] 
    [2022-01-08 01:01:45.321] DBG: WatchDog counter value = 26
    [2022-01-08 01:01:45.321] DBG: WatchDog reset status = 0
    [2022-01-08 01:01:45.321] DBG: Sys control and status register = 5
    [2022-01-08 01:01:45.321] DBG: WatchDog KEY register = 7
    [2022-01-08 01:01:45.338] DBG: WatchDog status register = E07
    [2022-01-08 01:01:45.338] DBG: WatchDog Windowed status register = 0
    [2022-01-08 01:01:45.360] 
    [2022-01-08 01:01:45.360] 
    [2022-01-08 01:01:45.360] test>pm,r,d
    [2022-01-08 01:01:45.938] 
    [2022-01-08 01:01:45.938] DBG: WatchDog counter value = 29
    [2022-01-08 01:01:45.938] DBG: WatchDog reset status = 0
    [2022-01-08 01:01:45.955] DBG: Sys control and status register = 5
    [2022-01-08 01:01:45.955] DBG: WatchDog KEY register = 7
    [2022-01-08 01:01:45.955] DBG: WatchDog status register = E07
    [2022-01-08 01:01:45.961] DBG: WatchDog Windowed status register = 0
    [2022-01-08 01:01:45.961] 
    [2022-01-08 01:01:45.961] 
    [2022-01-08 01:01:45.961] test>pm,r,d
    [2022-01-08 01:01:46.538] 
    [2022-01-08 01:01:46.538] DBG: WatchDog counter value = 3
    [2022-01-08 01:01:46.538] DBG: WatchDog reset status = 0
    [2022-01-08 01:01:46.555] DBG: Sys control and status register = 5
    [2022-01-08 01:01:46.555] DBG: WatchDog KEY register = 7
    [2022-01-08 01:01:46.572] DBG: WatchDog status register = E07
    [2022-01-08 01:01:46.572] DBG: WatchDog Windowed status register = 0
    [2022-01-08 01:01:46.572] 
    [2022-01-08 01:01:46.572] 
    [2022-01-08 01:01:46.572] test>pm,r,d
    [2022-01-08 01:01:47.222] 
    [2022-01-08 01:01:47.222] DBG: WatchDog counter value = 86
    [2022-01-08 01:01:47.238] DBG: WatchDog reset status = 0
    [2022-01-08 01:01:47.238] DBG: Sys control and status register = 5
    [2022-01-08 01:01:47.255] DBG: WatchDog KEY register = 7
    [2022-01-08 01:01:47.255] DBG: WatchDog status register = E07
    [2022-01-08 01:01:47.255] DBG: WatchDog Windowed status register = 0
    [2022-01-08 01:01:47.255] 
    [2022-01-08 01:01:47.255] 
    [2022-01-08 01:01:47.255] test>pm,r,d
    [2022-01-08 01:01:47.805] 
    [2022-01-08 01:01:47.805] DBG: WatchDog counter value = 39
    [2022-01-08 01:01:47.821] DBG: WatchDog reset status = 0
    [2022-01-08 01:01:47.821] DBG: Sys control and status register = 5
    [2022-01-08 01:01:47.821] DBG: WatchDog KEY register = 7
    [2022-01-08 01:01:47.838] DBG: WatchDog status register = E07
    [2022-01-08 01:01:47.838] DBG: WatchDog Windowed status register = 0
    [2022-01-08 01:01:47.838] 
    [2022-01-08 01:01:47.838] 
    [2022-01-08 01:01:47.838] test>pm,r,d
    [2022-01-08 01:01:48.452] 
    [2022-01-08 01:01:48.452] DBG: WatchDog counter value = 64
    [2022-01-08 01:01:48.452] DBG: WatchDog reset status = 0
    [2022-01-08 01:01:48.452] DBG: Sys control and status register = 5
    [2022-01-08 01:01:48.467] DBG: WatchDog KEY register = 7
    [2022-01-08 01:01:48.471] DBG: WatchDog status register = E07
    [2022-01-08 01:01:48.471] DBG: WatchDog Windowed status register = 0
    [2022-01-08 01:01:48.488] 
    [2022-01-08 01:01:48.488] 
    [2022-01-08 01:01:48.488] test>pm,r,d
    [2022-01-08 01:01:49.073] 
    [2022-01-08 01:01:49.073] DBG: WatchDog counter value = 59
    [2022-01-08 01:01:49.073] DBG: WatchDog reset status = 0
    [2022-01-08 01:01:49.073] DBG: Sys control and status register = 5
    [2022-01-08 01:01:49.073] DBG: WatchDog KEY register = 7
    [2022-01-08 01:01:49.088] DBG: WatchDog status register = E07
    [2022-01-08 01:01:49.088] DBG: WatchDog Windowed status register = 0
    [2022-01-08 01:01:49.088] 
    [2022-01-08 01:01:49.088] 
    [2022-01-08 01:01:49.088] test>pm,r,d
    [2022-01-08 01:01:49.795] 
    [2022-01-08 01:01:49.795] DBG: WatchDog counter value = 182
    [2022-01-08 01:01:49.795] DBG: WatchDog reset status = 0
    [2022-01-08 01:01:49.795] DBG: Sys control and status register = 5
    [2022-01-08 01:01:49.805] DBG: WatchDog KEY register = 7
    [2022-01-08 01:01:49.805] DBG: WatchDog status register = E07
    [2022-01-08 01:01:49.822] DBG: WatchDog Windowed status register = 0
    [2022-01-08 01:01:49.822] 
    [2022-01-08 01:01:49.822] 
    [2022-01-08 01:01:49.822] test>pm,r,d
    [2022-01-08 01:01:50.404] 
    [2022-01-08 01:01:50.404] DBG: WatchDog counter value = 165
    [2022-01-08 01:01:50.405] DBG: WatchDog reset status = 0
    [2022-01-08 01:01:50.405] DBG: Sys control and status register = 5
    [2022-01-08 01:01:50.421] DBG: WatchDog KEY register = 7
    [2022-01-08 01:01:50.421] DBG: WatchDog status register = E07
    [2022-01-08 01:01:50.421] DBG: WatchDog Windowed status register = 0
    [2022-01-08 01:01:50.421] 
    [2022-01-08 01:01:50.421] 
    [2022-01-08 01:01:50.421] test>pm,r,d
    [2022-01-08 01:01:51.082] 
    [2022-01-08 01:01:51.082] DBG: WatchDog counter value = 238
    [2022-01-08 01:01:51.088] DBG: WatchDog reset status = 0
    [2022-01-08 01:01:51.088] DBG: Sys control and status register = 5
    [2022-01-08 01:01:51.105] DBG: WatchDog KEY register = 7
    [2022-01-08 01:01:51.105] DBG: WatchDog status register = E07
    [2022-01-08 01:01:51.105] DBG: WatchDog Windowed status register = 0
    [2022-01-08 01:01:51.105] 
    [2022-01-08 01:01:51.105] 
    [2022-01-08 01:01:51.105] test>pm,r,d
    [2022-01-08 01:01:51.689] 
    [2022-01-08 01:01:51.689] DBG: WatchDog counter value = 232
    [2022-01-08 01:01:51.705] DBG: WatchDog reset status = 0
    [2022-01-08 01:01:51.705] DBG: Sys control and status register = 5
    [2022-01-08 01:01:51.705] DBG: WatchDog KEY register = 7
    [2022-01-08 01:01:51.722] DBG: WatchDog status register = E07
    [2022-01-08 01:01:51.722] DBG: WatchDog Windowed status register = 0
    [2022-01-08 01:01:51.722] 
    [2022-01-08 01:01:51.722] 
    [2022-01-08 01:01:51.722] test>

  • And just to make triple sure, that there is not some code pointer somewhere calling the serviceWatchdog function in driverlib, i went in and changed the defines for the key's so a call to this would fail. As expected this made no difference at all.

  • Hi Martin,

    I am not sure how are you printing the WD configuration value. Are you running it in continuous loop ? I see some time the count value is decreasing instead of increasing e.g. it went from 16 to 1 and the later from 215 to 209. Any idea why it's like this.

    Can you also check in your code if WD counter ever reaches 0xFF value ? Basically you can just read the counter register in a loop and when ever it's value is 0xFF, print out all the settings including counter value.

    Regards,

    Vivek Singh

  • I have a test monitor running on the target where i can type in commands

    test>

    Is the prompt from trestmonitor

    pm,r,d

    Is the command i typed in

     

    DBG: WatchDog counter value = 232
    DBG: WatchDog reset status = 0
    DBG: Sys control and status register = 5
    DBG: WatchDog KEY register = 7
    DBG: WatchDog status register = E07
    DBG: WatchDog Windowed status register = 0

    Is the response from the test monitor.

    As you see from the timestamps (added by teraterm logger) there is 5 to 1 secconds between those commands, so it is exspected for the counter to rollover in the meantime, it is configured to reach max after 209 mS.

    I will do the suggested test and return.

  • Ok, got it. Also if you are able to scope the XRSn pin on board, please share the waveform of that as well.

  • I did the suggested test, i ended up using gpios to not mess up timming with the serial print of log_debug

    I ran this code:

        while( 1 )
        {
            if( 0xFF == SysCtl_getWatchdogCounterValue())
            {
                GPIO_writePin( RELAY_2_PIN, 1 );
    //            Log_debug("W\r\n");
            }
            else
            {
                GPIO_writePin( RELAY_2_PIN, 0 );
            }
            if( 0x00 == SysCtl_getWatchdogCounterValue())
            {
                GPIO_writePin( RELAY_1_PIN, 1 );
    //            Log_debug("0\r\n");
            }
            else
            {
                GPIO_writePin( RELAY_1_PIN, 0 );
    //            Log_debug("0\r\n");
            }
        }

    From this I extracted these scope dumps

    Ch1: (orange) is RELAY_2_PIN from above code

    Ch2 (bluish) . is RELAY_1_PIN from above code

    Period of 0xFF and 0x00

    watchdog period measurement

    My conclusion is that the counter is running as expected.

    I will return with the XRSn measurement.

  • Here is the XRSn pin, the picture is taken from one of the times where the WD managed to reset the cpu, when it stops doing this the XRSn also goes total silence.

    XRSn pin on WD reset

    I read a pull down time of 40 µs this is way less than you would exspect from the readings in sysConfig

    The connections to XRSn

    Note IC700 is not mounted, it was put in the schematic to alocate space on pcb if we later find that ecternal reset is needed.

    So XRSn is only connected to the R701 and C700, we don't use it to reset any other device.

  • Martin,

    I read a pull down time of 40 µs this is way less than you would exspect from the readings in sysConfig

    WDCLK here is INTOSC1 which is 10MHz (not the one you are showing) so low pulse should be 51.2uS or high. 

    I am assuming you are trying this on your custom board. If you have a TI board can you try this on that and see if you still have this issue ? If you see same issue then I'll take your sample code and try to re-produce it on my setup here.

    Regards,

    Vivek Singh

  • Well the 40 µs is from just looking at the not so noise free graph, so 51 sounds within the reading uncetanty.

    But besides that I am not worried about this duration, we do not use this signal for anything, it just struck me that it was so far off from what sysconfig has calculated, looks like a bug in sysconfig.

    Regarding the port to a TI board, yes this was measured on our own board, the same as i posted schematic from.

    I did do a quick test on a ti board yesterday, but that did not show the error, so need further investigation. And I am on a very tight schedule right now, so don'r know if I will be able to do that.

    Regarding the TI board, we are using the f280023 and the launchpad uses the f280025c (don't think i can get a launchpad with the f280023). How similar is the silicon on those two chips?

  • Thanks Martin.

    Regarding the TI board, we are using the f280023 and the launchpad uses the f280025c (don't think i can get a launchpad with the f280023). How similar is the silicon on those two chips?

    Both are same so no issue in using either of them.

    Regards,

    Vivek Singh

  • Hi

    I spent most of today on scraping it down to a minimum, but now i have a set of files that will show the error on a LUNCHXL-F280025C.

    I can quote the main part of the source here, but if that is not sufficient for you to reproduce, please advice how I sent all files to you.

    I made a small main that will first turn on the red LED for a short while, after that it starts flashing the green LED.

    That means a blink from the red LED indicates that a reset just happened, and a blinking green LED indicated the main loop running.

    What i observe when i run this program is that the red LED blinks indicating the Watchdog working, but after a while (2-30 seconds) the red LED stops and only the green is blinking, indicating the watchdog stopped working and main loop running.

    The Delay before the WATCHDOG_init() has a significant influence on this fault.I have experiemntet with moving the delay around and/or changing the delay.

     Device_init() is almost unchanged from the example project in  C200Ware we used as offset, you can use led_ex1_blibky.

    Main snippet:

    #include "device.h"
    #include "driverlib/sysctl.h"
    #include "driverlib/gpio.h"
    #include "driverlib/interrupt.h"
    
    /// @privatesection
    // ---------------- Local constants (#define) ---------------------------------
    
    // LEDs
    #define DEVICE_GPIO_PIN_RED_LED        31U             // GPIO number for LED4
    #define DEVICE_GPIO_PIN_GREEN_LED      34U             // GPIO number for LED5
    
    /// @privatesection
    // ---------------- Local type declarations (typedef) -------------------------
    
    /// @privatesection
    // ---------------- Local data definitions (static) ---------------------------
    
    /// @privatesection
    // ---------------- Local function declarations (static) ----------------------
    static void WATCHDOG_init();
    
    /// @publicsection
    // ---------------- Public function definitions (implementation) --------------
    
    
    
    /**
     * @brief   Entry point of the powermicro software.
     */
    void main( void )
    {
        // Initialize device clock and peripherals
        Device_init();
    
        // Initialize GPIO and configure GPIO pins for CANTX/CANRX
        GPIO_setPadConfig(DEVICE_GPIO_PIN_RED_LED, GPIO_PIN_TYPE_STD);
        GPIO_setDirectionMode(DEVICE_GPIO_PIN_RED_LED, GPIO_DIR_MODE_OUT);
        GPIO_setPadConfig(DEVICE_GPIO_PIN_GREEN_LED, GPIO_PIN_TYPE_STD);
        GPIO_setDirectionMode(DEVICE_GPIO_PIN_GREEN_LED, GPIO_DIR_MODE_OUT);
    
    
    
        // Board initialization
        // This is not needed but it makes the fault happen way more frequent, without it you may need to wait for an hour or more ??
        // This delay was originally part of the ADC_init also generated by sysconfig, (adc setup need to wait for a voltage regulator to stabelize)
        DEVICE_DELAY_US(5000);
        EALLOW;
        WATCHDOG_init();
        EDIS;
    
        GPIO_writePin(DEVICE_GPIO_PIN_RED_LED, 0);
        DEVICE_DELAY_US(50 * 1000L);
        GPIO_writePin(DEVICE_GPIO_PIN_RED_LED, 1);
        for(;;)
        {
    
            // Turn on LED
            GPIO_writePin(DEVICE_GPIO_PIN_GREEN_LED, 0);
    
            // Delay for a bit.
            DEVICE_DELAY_US(50 * 1000L);
    
            // Turn off LED
            GPIO_writePin(DEVICE_GPIO_PIN_GREEN_LED, 1);
    
            // Delay for a bit.
            DEVICE_DELAY_US(50 * 1000L);
        }
    }
    
    /// @privatesection
    // ---------------- Local function definitions (static implementation) ---------------
    
    /**
     * Copied from sysconfig generated code
     */
    static void WATCHDOG_init(){
        //WATCHDOG initialization
    //    EALLOW;
        SysCtl_disableWatchdog();
        SysCtl_setWatchdogMode(SYSCTL_WD_MODE_RESET);
        SysCtl_setWatchdogPredivider(SYSCTL_WD_PREDIV_128);
        SysCtl_setWatchdogPrescaler(SYSCTL_WD_PRESCALE_64);
        SysCtl_setWatchdogWindowValue(0);
        SysCtl_enableWatchdog();
    //    EDIS;
    }
    

  • Hi Martin,

    I tried your project on a LAUNCHXL-F280025C, but am not able to reproduce the issue (i.e. always see red blinking). Can you share your 'Device_init();' function? I think that's the only thing that could be different.

    Best,

    Kevin

  • Don't think it is the device init, it is the same as the one the blink example. But maybe the linker file.

    Is there a way I can send you the whole project as a zip?

    MEMORY
    {
    // Mx Ram, Dedicated CPU ram.
       BEGIN             : origin = 0x080000,   length = 0x00000002
       BOOT_RSVD         : origin = 0x00000002, length = 0x00000126
       RAMMx             : origin = 0x00000128, length = 0x000006D0
    // RAMMx_RSVD        : origin = 0x000007F8, length = 0x00000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
    
       /* Local Shared RAM, shared to CPU, HIC and BGCRC */
       RAMLS             : origin = 0x0000A000, length = 0x00002000
       /* Global Shared RAM, shared to CPU, HIC and DMA */
       RAMGS            : origin = 0x0000C000, length = 0x000007F8
    // RAMGS_RSVD       : origin = 0x0000C7F8, length = 0x00000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
    
    // PIE_VECTOR_TABLE  : origin = 0x0000D000, length = 0x00000200
    
    // TI_OTP            : origin = 0x00070000, length = 0x00000400
    // DCSM_OTP          : origin = 0x00078000, length = 0x00000400
    
       /* on-chip Flash */
       FLASH_BANK0       : origin = 0x00080002, length = 0x00007FEE
    // FLASH_BANK0_RSVD  : origin = 0x0008FFF0, length = 0x00000010 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
    
       BOOT_ROM          : origin = 0x003F0000, length = 0x00008000
       BOOT_ROM_EXT      : origin = 0x003F8000, length = 0x00007FC0
       RESET             : origin = 0x003FFFC0, length = 0x00000002
    }
    
    
    SECTIONS
    {
       codestart        : > BEGIN,           ALIGN(8)
       .text            : > FLASH_BANK0,     ALIGN(8)
       .cinit           : > FLASH_BANK0,     ALIGN(8)
       .switch          : > FLASH_BANK0,     ALIGN(8)
       .reset           : > RESET,           TYPE = DSECT /* not used, */
    
       .stack           : > RAMMx
    
       .init_array      : > FLASH_BANK0,     ALIGN(8)
       .bss             : >> RAMLS | RAMGS
       .bss:output      : >> RAMLS | RAMGS
       .bss:cio         : >> RAMLS | RAMGS
       .const           : > FLASH_BANK0,     ALIGN(8)
       .data            : >> RAMLS | RAMGS
       .sysmem          : > RAMLS | RAMGS
    
    //    ramgs0 : > RAMGS0
    
        /*  Allocate IQ math areas: */
    //   IQmath           : > RAMLS
    //   IQmathTables     : > RAMLS
    
    
      .TI.ramfunc      : LOAD = FLASH_BANK0,
                      RUN = RAMGS,
                      LOAD_START(RamfuncsLoadStart),
                      LOAD_SIZE(RamfuncsLoadSize),
                      LOAD_END(RamfuncsLoadEnd),
                      RUN_START(RamfuncsRunStart),
                      RUN_SIZE(RamfuncsRunSize),
                      RUN_END(RamfuncsRunEnd),
                      ALIGN(8)
    
    }
    /*
    //===========================================================================
    // End of file.
    //===========================================================================
    */
    

    //#############################################################################
    // $TI Release: F28002x Support Library v3.04.00.00 $
    // $Release Date: Fri Feb 12 18:58:34 IST 2021 $
    // $Copyright:
    // Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
    //
    // Redistribution and use in source and binary forms, with or without 
    // modification, are permitted provided that the following conditions 
    // are met:
    // 
    //   Redistributions of source code must retain the above copyright 
    //   notice, this list of conditions and the following disclaimer.
    // 
    //   Redistributions in binary form must reproduce the above copyright
    //   notice, this list of conditions and the following disclaimer in the 
    //   documentation and/or other materials provided with the   
    //   distribution.
    // 
    //   Neither the name of Texas Instruments Incorporated nor the names of
    //   its contributors may be used to endorse or promote products derived
    //   from this software without specific prior written permission.
    // 
    // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
    // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
    // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
    // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
    // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
    // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
    // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
    // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
    // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
    // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
    // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
    // $
    //#############################################################################
    
    /**
     * @copyright Confidential property of Danfoss Drives A/S 2021-2022. All Rights Reserved.
     * @copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
     *
     * @defgroup DEVICE TMS32F28002x device module.
     * @{
     * @brief Collection of device specific functions for TMS32F28002x micro controllers.
     * @inlayer HA_LAYER
     *
     * @file
     */
    
    // ---------------- Dependencies (#include) needed by the implementation ------
    #include "device.h" // Always my own interface first
    #include "driverlib/sysctl.h"
    #include "driverlib/asysctl.h"
    #include "driverlib/flash.h"
    #include "driverlib/gpio.h"
    
    #ifdef __cplusplus
    using std::memcpy;
    #endif
    
    /// @privatesection
    // ---------------- Local constants (#define) ---------------------------------
    
    /// @privatesection
    // ---------------- Local type declarations (typedef) -------------------------
    
    /// @privatesection
    // ---------------- Local data definitions (static) ---------------------------
    
    /// @privatesection
    // ---------------- Local function declarations (static) ----------------------
    
    /// @publicsection
    // ---------------- Public function definitions (implementation) --------------
    
    /** @brief Initialize the device.
     *  Primarily initializes system control to a known state by disabling the watchdog,
     *  setting up the SYSCLKOUT frequency, and enabling the clocks to the peripherals.
     */
    void Device_init( void )
    {
        // Disable the watchdog
        SysCtl_disableWatchdog();
    
    #ifdef _FLASH
        // Copy time critical code and flash setup code to RAM. This includes the
        // following functions: InitFlash();
        //
        // The RamfuncsLoadStart, RamfuncsLoadSize, and RamfuncsRunStart symbols
        // are created by the linker. Refer to the device .cmd file.
        memcpy( &RamfuncsRunStart, &RamfuncsLoadStart, (size_t)&RamfuncsLoadSize );
    
        // Call Flash Initialization to setup flash waitstates. This function must
        // reside in RAM.
        Flash_initModule( FLASH0CTRL_BASE, FLASH0ECC_BASE, DEVICE_FLASH_WAITSTATES );
    #endif
    
        // Set up PLL control and clock dividers
        SysCtl_setClock( DEVICE_SETCLOCK_CFG );
    
        // Make sure the LSPCLK divider is set to the default (divide by 4)
        SysCtl_setLowSpeedClock( SYSCTL_LSPCLK_PRESCALE_4 );
    
        // These asserts will check that the #defines for the clock rates in
        // device.h match the actual rates that have been configured. If they do
        // not match, check that the calculations of DEVICE_SYSCLK_FREQ and
        // DEVICE_LSPCLK_FREQ are accurate. Some examples will not perform as
        // expected if these are not correct.
        ASSERT( SysCtl_getClock(DEVICE_OSCSRC_FREQ) == DEVICE_SYSCLK_FREQ );
        ASSERT( SysCtl_getLowSpeedClock(DEVICE_OSCSRC_FREQ) == DEVICE_LSPCLK_FREQ );
    
    #ifndef _FLASH
        //
        // Call Device_cal function when run using debugger
        // This function is called as part of the Boot code. The function is called
        // in the Device_init function since during debug time resets, the boot code
        // will not be executed and the gel script will reinitialize all the
        // registers and the calibrated values will be lost.
        // Sysctl_deviceCal is a wrapper function for Device_Cal
        //
        SysCtl_deviceCal();
    #endif
    
        // Turn on all peripherals
        Device_enableAllPeripherals();
    
        // Lock VREGCTL Register
        // The register VREGCTL is not supported in this device. It is locked to
        // prevent any writes to this register
        ASysCtl_lockVREG();
    }
    
    /**
     * @brief Turn on all peripherals.
     *  enabling the clock to the peripherals' registers.
     *
     *  @note That to reduce power, unused peripherals could be disabled.<br>
     *        But this is not a battery powered device so we let them all be on.
     */
    void Device_enableAllPeripherals( void )
    {
        SysCtl_enablePeripheral( SYSCTL_PERIPH_CLK_DMA );
        SysCtl_enablePeripheral( SYSCTL_PERIPH_CLK_TIMER0 );
        SysCtl_enablePeripheral( SYSCTL_PERIPH_CLK_TIMER1 );
        SysCtl_enablePeripheral( SYSCTL_PERIPH_CLK_TIMER2 );
        SysCtl_enablePeripheral( SYSCTL_PERIPH_CLK_CPUBGCRC );
        SysCtl_enablePeripheral( SYSCTL_PERIPH_CLK_HRCAL );
        SysCtl_enablePeripheral( SYSCTL_PERIPH_CLK_TBCLKSYNC );
        SysCtl_enablePeripheral( SYSCTL_PERIPH_CLK_ERAD );
    
        SysCtl_enablePeripheral( SYSCTL_PERIPH_CLK_EPWM1 );
        SysCtl_enablePeripheral( SYSCTL_PERIPH_CLK_EPWM2 );
        SysCtl_enablePeripheral( SYSCTL_PERIPH_CLK_EPWM3 );
        SysCtl_enablePeripheral( SYSCTL_PERIPH_CLK_EPWM4 );
        SysCtl_enablePeripheral( SYSCTL_PERIPH_CLK_EPWM5 );
        SysCtl_enablePeripheral( SYSCTL_PERIPH_CLK_EPWM6 );
        SysCtl_enablePeripheral( SYSCTL_PERIPH_CLK_EPWM7 );
    
        SysCtl_enablePeripheral( SYSCTL_PERIPH_CLK_ECAP1 );
        SysCtl_enablePeripheral( SYSCTL_PERIPH_CLK_ECAP2 );
        SysCtl_enablePeripheral( SYSCTL_PERIPH_CLK_ECAP3 );
    
        SysCtl_enablePeripheral( SYSCTL_PERIPH_CLK_EQEP1 );
        SysCtl_enablePeripheral( SYSCTL_PERIPH_CLK_EQEP2 );
    
        SysCtl_enablePeripheral( SYSCTL_PERIPH_CLK_SCIA );
    
        SysCtl_enablePeripheral( SYSCTL_PERIPH_CLK_SPIA );
        SysCtl_enablePeripheral( SYSCTL_PERIPH_CLK_SPIB );
    
        SysCtl_enablePeripheral( SYSCTL_PERIPH_CLK_I2CA );
        SysCtl_enablePeripheral( SYSCTL_PERIPH_CLK_I2CB );
    
        SysCtl_enablePeripheral( SYSCTL_PERIPH_CLK_CANA );
    
        SysCtl_enablePeripheral( SYSCTL_PERIPH_CLK_ADCA );
        SysCtl_enablePeripheral( SYSCTL_PERIPH_CLK_ADCC );
    
        SysCtl_enablePeripheral( SYSCTL_PERIPH_CLK_CMPSS1 );
        SysCtl_enablePeripheral( SYSCTL_PERIPH_CLK_CMPSS2 );
        SysCtl_enablePeripheral( SYSCTL_PERIPH_CLK_CMPSS3 );
        SysCtl_enablePeripheral( SYSCTL_PERIPH_CLK_CMPSS4 );
    
        SysCtl_enablePeripheral( SYSCTL_PERIPH_CLK_FSITXA );
        SysCtl_enablePeripheral( SYSCTL_PERIPH_CLK_FSIRXA );
    
        SysCtl_enablePeripheral( SYSCTL_PERIPH_CLK_LINA );
        SysCtl_enablePeripheral( SYSCTL_PERIPH_CLK_LINB );
    
        SysCtl_enablePeripheral( SYSCTL_PERIPH_CLK_PMBUSA );
    
        SysCtl_enablePeripheral( SYSCTL_PERIPH_CLK_DCC0 );
        SysCtl_enablePeripheral( SYSCTL_PERIPH_CLK_DCC1 );
    
        SysCtl_enablePeripheral( SYSCTL_PERIPH_CLK_CLB1 );
        SysCtl_enablePeripheral( SYSCTL_PERIPH_CLK_CLB2 );
    
        SysCtl_enablePeripheral( SYSCTL_PERIPH_CLK_HICA );
    }
    
    /**
     *  @brief Disable pin locks on GPIOs.
     */
    void Device_initGPIO( void )
    {
        // Disable pin locks.
        GPIO_unlockPortConfig( GPIO_PORT_A, 0xFFFFFFFF );
        GPIO_unlockPortConfig( GPIO_PORT_B, 0xFFFFFFFF );
        GPIO_unlockPortConfig( GPIO_PORT_H, 0xFFFFFFFF );
    }
    
    /** @brief Error handling function to be called when an ASSERT is violated
     *
     * @param filename File name in which the error has occurred
     * @param line Line number within the file
     */
    void __error__( char *filename, uint32_t line )
    {
        (void)filename;
        (void)line;
        // An ASSERT condition was evaluated as false. You can use the filename and
        // line parameters to determine what went wrong.
        ESTOP0;
    }
    
    /// @privatesection
    // ---------------- Local function definitions (implementation) ---------------
    
    /** @} group*/
    

    Trying to also add the header but got this

    Access Denied

    You don't have permission to access "">e2e.ti.com/.../configure on this server.

    Reference #18.7c85655f.1642019252.aad9419

  • Trying with header in new post

    Nope still get

    Access Denied

    You don't have permission to access "">e2e.ti.com/.../configure on this server.

    Reference #18.7c85655f.1642019332.aaee0b9

    Would save us all some time if I could upload the project somewhere.

  • Martin, 

    You should be able to export the project file and send the zip file. 

    Regards,

    Vivek Singh

  • Hi Martin,

    I tried with the linker CMD and device.c files you provided, but I'm still not able to reproduce the issue.

    As Vivek mentioned, you can directly export a zip file in CCS by right clicking the project name --> select Export --> go through dialog.

    Best,

    Kevin

  • My problem is not creating the file, but where/how to send it. Maybe the Forrest is blocking my view of the trees, but i can't find anywhere here to attach a file to this case, i tried clicking on one of your names to see if i could send a file that way but did not find a way.

  • Hi

    Just in case this turns out to be a batch thing, I include a picture of the lunchpad chip here.

    F280025c

  • Since you are observing this issue on your board as well as on launchpad, I don't think this issue is specific to batch. 

  • Martin,

    Can you try Insert --> Image/video/file --> choose your zip.

    Best,

    Kevin

  • That's a hack ;-)  I will try

    WD_fail__mao_at_danfoss_com.zip

    Seams to work

    You will find the project in:

    \watchdog_fault\product\powermicro\lowPower\

    Some strange paths, I know, but it is the remains of a gutted project Wink

  • Hi Martin,

    Thanks for uploading.

    I tried your project as is, but it didn't run standalone from Flash properly. After adding '_FLASH' to the Predefined Symbols it seems to work properly.

    Can you check that this symbol is defined in your project? It gets referenced in Device_init() for copying code from Flash to RAM.

    Best,

    Kevin

  • Please use the default configuration, despite the naming.

  • Also I zipped the entire folder structure, so inside the default folder you will find the binary that came out of my compiler for reference.

  • Hi Martin,

    I tried the 'default' config and I can reproduce your issue. Now to figure out what the cause is.

    Do you know of any specific differences you made between the working 'default_launchpad' config and the non-working 'default' config? I'll look into the 'default' config some more.

    Best,

    Kevin

  • I can reproduce your issue

    Hurray :-)

    I have not used the 'default_launchpad' config for a long time, i thought i had removed it, it is a remenence of early project startup before we got our own hardware. So please ignore this.

    As I mention in the source, the delay before i init the watchdog seems to have a high influence on the fault.

  • Hi Martin,

    I believe it's related to the optimization settings of the CCS project. I tried the below settings and it seems to work, please try as well.

    I found this by comparing the compiler settings of the 'default_launchpad' and 'default' configs.

    Best,

    Kevin

  • I can confirm the optimatation setting has an influence on the problem.

    I was running at opt level 1, seeing the problem after 10-100 resets.

    If i try your suggestion of opt level off, i have seen the problem so far.

    but the funny thing is that if I set the opt level to 0, the problem ocurs fast, that is whitin 0-2 resets, i actually have toi manually reset a few times until i see a watchdog reset happen.

    I tried setting the optimization level on individual files, and it apears that if project is set to opt = offf, and i set powermicro.c to opt = 1 the error returns.

    All this just do not explain why is behaves different between resets. But it hopefully gives you something to go with.

  • Hi Martin,

    We reviewed the optimized code and found that inside WATCHDOG_init function all the writes to register had EALLOW and EDIS code which optimization removes and replaces with one EALLOW followed by all register writes and then EDIS. This creates back-to-back write to WDCR register which has some restriction hence it creates issue. I have inserted few NOPS before WD enable code and this fixed the issue.

    Please see below snapshot of the code -

    Regards,

    Vivek Singh

  • Looks great, I think this is a viable conclusion, and can explain why it differs between resets.

    What I would prefer from TI now, is that You get in touch with some of the chip designers to

    1. Confirm this as the issue
    2. A more detailed instruction on how to set these registers,
      1. Is 8 NOP's sufficient in all cases, or are just lucky here?
      2. Is there any status registers where I am able to detect this fault state?
    3. Get the above in the manual or an errata sheet.

    And when the correct algorithm for setting these registers is knwon change syslib to adhere to this.

    FYI. From your solution i made a similar change to my code and it has been running for a few hours now, with no fault.

    static void WATCHDOG_init(){
        //WATCHDOG initialization
        EALLOW;
        SysCtl_disableWatchdog();
        SysCtl_setWatchdogMode(SYSCTL_WD_MODE_RESET);
        SysCtl_setWatchdogPredivider(SYSCTL_WD_PREDIV_128);
        SysCtl_setWatchdogPrescaler(SYSCTL_WD_PRESCALE_64);
        SysCtl_setWatchdogWindowValue(0);
        SysCtl_delay(10);
        SysCtl_enableWatchdog();
        EDIS;
    }
    

    Main difference I use the SysCtl_delay function.

  • Hi Martin,

    Confirm this as the issue

    Yes, this is an issue and we have pending action on this one to update our document and SW for this. 

    Is 8 NOP's sufficient in all cases, or are just lucky here?

    We'll get this info and update.

    Is there any status registers where I am able to detect this fault state?

    No, there is no status register for this to know. This is one of those error which we need to prevent and make sure it does not happen.

    Main difference I use the SysCtl_delay function.

    This is ok (equivalent to 50+ cycle) but once we confirm the min number of cycle, you can update it.

    Regards,

    Vivek Singh

  • Hi Martin,

    This is about minimum number of cycle needed between back-2-back writes -

    It's 39 cycle and you have 50+ cycle if delay so this should be ok.

    Regards,

    Vivek Singh

  • Sounds good.

    Can you give just a little more technical details to why this is, I need to have something to back up this claim in order to sell this solution internally too.

  • Hi Martin,

    Please see if below info helps -

    This info will be added in device documentation. 

    Regards,

    Vivek Singh

  • That did resolve my issue, thankyou.

    However I have suggestion for your new text, You already refer a lot to driverlib functions in the manual, so i suggest you include the use of sysctl_delay in here. Also because insertion of assembler commands like NOP, can affect the optimizer, acording tothe C200 compiler manual.

    I also see this reflected by the compiler:

    If I use `asm("  NOP");` i get this remark from the compiler

    #1463-D Link-time optimization is disabled for this file due to the use of inline assembly    WatchDog.c

    If i use SysCtl_delay() I get no remarks.

    However my issue is solved, this was just a friendly input. :-)

  • Thank you for the input Martin. I'll pass it to our software team. 

    If I use `asm("  NOP");` i get this remark from the compiler

    #1463-D Link-time optimization is disabled for this file due to the use of inline assembly    WatchDog.c

    I don't see this warning though. Are you getting this as warning or in compiler log ?

    Regards,

    Vivek Singh

  • It is not a warning, but a remark.

    And it is only remarked when you enable optlevel 4 link time optimization.

    So it not a big issue, but it can cost some performance.

    I was just doing some optimization on my serial queue handling, and at some point i tried using DINT instead of Sci_disableInterrupt(), suddenly my performance in there dropped significantly, and the explanation was fund in that remark.

  • One could consider if this remark is placed correctly

    I would say that is an optimization advice, but that is a discussion for another day ;-)

  • Ok, thank you.

    Regards,

    Vivek Singh