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TMS320F280025: PLLSYSCLKDIV_LSB in SYSCLKDIVSEL Register

Irene Boben
Expert 1030 points

Part Number: TMS320F280025

Hi Team,

I understand PLLSYSCLKDIV_LSB is used to have odd divisor values. However I could not see any API where this value is set.

Also if PLLSYSCLKDIV_LSB and PLLSYSCLKDIV are both 0, will the System Clock Divider be 1? 

  • 0
    TI__Genius 15385 points

    Hi,

    Below Set clock function inside driverlib takes the PLLSYSCLKDIV as input:

    //
        // Set up PLL control and clock dividers
        //
        SysCtl_setClock(DEVICE_SETCLOCK_CFG);

    Also DEVICE_SETCLOCK_CFG macro inputs SYSCLKDIV value:

    #define DEVICE_SETCLOCK_CFG          (SYSCTL_OSCSRC_XTAL | SYSCTL_IMULT(30) | \
                                          SYSCTL_REFDIV(2) | SYSCTL_ODIV(3) | \
                                          SYSCTL_SYSDIV(1) | SYSCTL_PLL_ENABLE | \
                                          SYSCTL_DCC_BASE_0)

    Your understanding is correct, if PLLSYSCLKDIV_LSB and PLLSYSCLKDIV both are 0 then SYSCLKDIV=1.

    Best Regards,

    Nirav

  • 0 in reply to Nirav Ginwala
    Expert 1030 points

    The TRM says 'The minimum value of this divider is 2 when PLL is enabled'. So the SYSCLKDIV = 1 will not be a valid value then?

  • 0 in reply to Irene Boben
    TI__Genius 15385 points

    Hi Irene,

    Now that we have ODIV, the comment of minimum divider required to be 2 is not valid. We will correct that in the next release.

    Thanks for bringing this to our attention.

    Best Regards,

    Nirav