TMS320F28377S: TMS320F28377S interrupt SCI

I am using the sci_loopback_interrupts example.
I am using the TR28377S kit, Chipset is TMS320F28377S, USB C-port
I want to check that data is coming through serial communication, but it doesn't work because the setting is wrong. what went wrong?

//###########################################################################
//
// FILE: Example_2837xSSci_FFDLB_int.c
//
// TITLE: SCI Digital Loop Back with Interrupts.
//
//! \addtogroup cpu01_example_list
//! <h1>SCI Digital Loop Back with Interrupts (sci_loopback_interrupts)</h1>
//!
//! This program uses the internal loop back test mode of the peripheral.
//! Other then boot mode pin configuration, no other hardware configuration
//! is required. Both interrupts and the SCI FIFOs are used.
//!
//! A stream of data is sent and then compared to the received stream.
//! The SCI-A sent data looks like this: \n
//! 00 01 \n
//! 01 02 \n
//! 02 03 \n
//! .... \n
//! FE FF \n
//! FF 00 \n
//! etc.. \n
//! The pattern is repeated forever.
//!
//! \b Watch \b Variables \n
//! - \b sdataA - Data being sent
//! - \b rdataA - Data received
//! - \b rdata_pointA - Keep track of where we are in the data stream.
//! This is used to check the incoming data
//!
//
//###########################################################################
//
// $Release Date: $
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//
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//###########################################################################

//
// Included Files
//
#include "F28x_Project.h"
#include <stdio.h> // ANSI C 표준입출력 함수용 헤더파일 삽입

//
// Defines
//
#define CPU_FREQ 60E6
#define LSPCLK_FREQ CPU_FREQ/2
#define SCI_FREQ 100E3
#define SCI_PRD ((LSPCLK_FREQ/(SCI_FREQ*8))-1)

//
// Globals
//
Uint16 sdataC[2]; // Send data for SCI-A
Uint16 rdataC[2]; // Received data for SCI-A
Uint16 rdata_pointA; // Used for checking the received data

//
// Function Prototypes
//
interrupt void scicTxFifoIsr(void);
interrupt void scicRxFifoIsr(void);
void scic_fifo_init(void);
void error(void);

//
// Main
//
void main(void)
{
Uint16 i;

//
// Step 1. Initialize System Control:
// PLL, WatchDog, enable Peripheral Clocks
// This example function is found in the F2837xS_SysCtrl.c file.
//
InitSysCtrl();

//
// Step 2. Initialize GPIO:
// This example function is found in the F2837xS_Gpio.c file and
// illustrates how to set the GPIO to it's default state.
//
InitGpio();

//
// For this example, only init the pins for the SCI-A port.
// GPIO_SetupPinMux() - Sets the GPxMUX1/2 and GPyMUX1/2 register bits
// GPIO_SetupPinOptions() - Sets the direction and configuration of the GPIOS
// These functions are found in the F2837xS_Gpio.c file.
//
GPIO_SetupPinMux(62, GPIO_MUX_CPU1, 1);
GPIO_SetupPinOptions(62, GPIO_INPUT, GPIO_PUSHPULL);
GPIO_SetupPinMux(63, GPIO_MUX_CPU1, 1);
GPIO_SetupPinOptions(63, GPIO_OUTPUT, GPIO_ASYNC);
//
// Step 3. Clear all interrupts and initialize PIE vector table:
// Disable CPU interrupts
//
DINT;

//
// Initialize PIE control registers to their default state.
// The default state is all PIE interrupts disabled and flags
// are cleared.
// This function is found in the F2837xS_PieCtrl.c file.
//
InitPieCtrl();

//
// Disable CPU interrupts and clear all CPU interrupt flags:
//
IER = 0x0000;
IFR = 0x0000;

//
// Initialize the PIE vector table with pointers to the shell Interrupt
// Service Routines (ISR).
// This will populate the entire table, even if the interrupt
// is not used in this example. This is useful for debug purposes.
// The shell ISR routines are found in F2837xS_DefaultIsr.c.
// This function is found in F2837xS_PieVect.c.
//
InitPieVectTable();

//
// Interrupts that are used in this example are re-mapped to
// ISR functions found within this file.
//
EALLOW; // This is needed to write to EALLOW protected registers
PieVectTable.SCIC_RX_INT = &scicRxFifoIsr;
PieVectTable.SCIC_TX_INT = &scicTxFifoIsr;
EDIS; // This is needed to disable write to EALLOW protected registers

//
// Step 4. Initialize the Device Peripherals:
//
scic_fifo_init(); // Init SCI-A

//
// Step 5. User specific code, enable interrupts:
//
// Init send data. After each transmission this data
// will be updated for the next transmission
//
for(i = 0; i<2; i++)
{
sdataC[i] = i;
}

rdata_pointA = sdataC[0];

//
// Enable interrupts required for this example
//
PieCtrlRegs.PIECTRL.bit.ENPIE = 1; // Enable the PIE block
PieCtrlRegs.PIEIER9.bit.INTx1 = 1; // PIE Group 9, INT1
PieCtrlRegs.PIEIER9.bit.INTx2 = 1; // PIE Group 9, INT2
IER = 0x100; // Enable CPU INT
EINT;

//
// Step 6. IDLE loop. Just sit and loop forever (optional):
//
for(;;);
}

//
// error - Function to halt debugger on error
//
void error(void)
{
asm(" ESTOP0"); // Test failed!! Stop!
for (;;);
}

//
// sciaTxFifoIsr - SCIA Transmit FIFO ISR
//
interrupt void scicTxFifoIsr(void)
{
Uint16 i;

for(i=0; i< 2; i++)
{
ScicRegs.SCITXBUF.all=sdataC[i]; // Send data
}

for(i=0; i< 2; i++) // Increment send data for next cycle
{
sdataC[i] = (sdataC[i]+1) & 0x00FF;
}

ScicRegs.SCIFFTX.bit.TXFFINTCLR=1; // Clear SCI Interrupt flag
PieCtrlRegs.PIEACK.all|=0x100; // Issue PIE ACK
}

//
// sciaRxFifoIsr - SCIA Receive FIFO ISR
//
interrupt void scicRxFifoIsr(void)
{
Uint16 i;

for(i=0;i<2;i++)
{
rdataC[i]=ScicRegs.SCIRXBUF.all; // Read data
}

for(i=0;i<2;i++) // Check received data
{
if(rdataC[i] != ( (rdata_pointA+i) & 0x00FF) )
{
error();
}
}

rdata_pointA = (rdata_pointA+1) & 0x00FF;

ScicRegs.SCIFFRX.bit.RXFFOVRCLR=1; // Clear Overflow flag
ScicRegs.SCIFFRX.bit.RXFFINTCLR=1; // Clear Interrupt flag

PieCtrlRegs.PIEACK.all|=0x100; // Issue PIE ack
}

//
// scia_fifo_init - Configure SCIA FIFO
//
void scic_fifo_init()
{
ScicRegs.SCICCR.all = 0x0007; // 1 stop bit, No loopback
// No parity,8 char bits,
// async mode, idle-line protocol
ScicRegs.SCICTL1.all = 0x0003; // enable TX, RX, internal SCICLK,
// Disable RX ERR, SLEEP, TXWAKE
ScicRegs.SCICTL2.all = 0x0003;
ScicRegs.SCICTL2.bit.TXINTENA = 1;
ScicRegs.SCICTL2.bit.RXBKINTENA = 1;

// ScicRegs.SCIHBAUD.all = ((uint16_t)SCI_PRD & 0xFF00U) >> 8U;
// ScicRegs.SCILBAUD.all = (uint16_t)SCI_PRD & 0x00FFU;

ScicRegs.SCIHBAUD.all = 0x0001;
ScicRegs.SCILBAUD.all = 0x0086;

ScicRegs.SCICCR.bit.LOOPBKENA = 1; // Enable loop back
ScicRegs.SCIFFTX.all = 0xE040;
ScicRegs.SCIFFRX.all = 0x2044;
ScicRegs.SCIFFCT.all = 0x00;

ScicRegs.SCICTL1.all = 0x0023; // Relinquish SCI from Reset
ScicRegs.SCIFFTX.bit.TXFIFORESET = 1;
ScicRegs.SCIFFRX.bit.RXFIFORESET = 1;
}

//
// End of file
//